Multiprocessor system, its control method, and information recording medium

A control method for controlling a multiprocessor system having a plurality of processing modules, including a predetermined number, being three or more, of processors, and a bus for relaying data transmission among the respective processing modules, comprising:

• a step of facilitating data transmission between the predetermined number of processors and a predetermined processing module among the plurality of processing modules via one or more of a plurality of data transmission paths comprised within the bus,
• a step of specifying at least one damaged processor among the predetermined number of processors;
• a step of selecting as a communication restricted processor subjected to communication restriction at least one of the processors connected to the bus at a position determined according to a position where the damaged processor is connected to the bus such that the at least one processor carries out data transmission with respect to the predetermined processing module, using a data transmission path, among the plurality of data transmission paths, different from a data transmission path to be used in data transmission from the damaged processor to the predetermined processing module;
• and
• a step of restricting data transmission by the communication restricted processor via the bus.

A non-transitory, computer readable information storage medium storing a program to be executed by a multiprocessor system having a plurality of processing modules, including a predetermined number, being three or more, of processors, and a bus, comprising a plurality of data transmission paths, for relaying data transmission among the respective processing modules, the program causing the multiprocessor system to function as:

• damaged processor specifying means for specifying at least one damaged processor among the predetermined number of processors;
• communication restricted processor selecting means for selecting as a communication restricted processor subjected to communication restriction at least one of the processors connected to the bus at a position determined according to a position where the damaged processor is connected to the bus such that the at least one processor carries out data transmission with respect to a predetermined processing module among the plurality of processing modules, using a data transmission path, among the plurality of data transmission paths, different from a data transmission path to be used in data transmission from the damaged processor to the predetermined processing module;
• and
• communication restriction means for restricting data transmission by the communication restricted processor via the bus.

A multiprocessor system, comprising:

• a plurality of processing modules, including a plurality of processors;
• a ring type bus for relaying data transmission among the respective processing modules;
• table storage means for storing a table providing association between a subset of processors which are some of the plurality of processors and a plurality of processor designation information items each designating any of the subset of processors;
• damaged processor specifying means for specifying at least one damaged processor among the plurality of processors;
• and
• table production means for producing the table such that the processor designation information items each designate any of the plurality of processors, excluding the damaged processor, according to a position where the damaged processor is connected to the ring type bus and a processor to be designated by each of the processor designation information items from among the plurality of processors, is determined according to a position at which each of the processors, excluding the damaged processor, is connected to the bus,
• wherein each of the subset of processors carries out, based on an application program including a plurality of predetermined processes each associated with any of the processor designation information items, and the table produced, the predetermined process associated with the processer designation information item designating that processor.

A control method for controlling a multiprocessor system having a plurality of processing modules, including a plurality of processors, and a ring type bus for relaying data transmission among the respective processing modules, comprising:

• a step of specifying at least one damaged processor among the plurality of processors;
• and
• a step of producing a table providing association between a subset of processors which are some of the plurality of processors and a plurality of processor designation information items each designating any of the subset of processors, such that the processor designation information items each designate any of the plurality of processors, excluding the damaged processor, according to a position where the damaged processor is connected to the ring type bus and a processor to be designated by each of the processor designation information items from among the plurality of processors, is determined according to a position at which each of the processors, excluding the damaged processor, is connected to the bus,
• wherein each of the subset of processors carries out, based on an application program including a plurality of predetermined processes each associated with any of the processor designation information items, and the table produced, the predetermined process associated with the processer designation information item designating that processor.

A non-transitory, computer readable information storage medium storing a program to be executed by a multiprocessor system having a plurality of processing modules, including a plurality of processors, and a ring type bus for relaying data transmission among the respective processing modules, the program causing the multiprocessor system to function as:

• damaged processor specifying means for specifying at least one damaged processor among the plurality of processors;
• and
• table production means for producing a table showing association between a subset of processors which are some of the plurality of processors and a plurality of processor designation information items each designating any of the subset of processors, such that the processor designation information items each designate any of the plurality of processors, excluding the damaged processor, according to a position where the damaged processor is connected to the ring type bus and a processor to be designated by each of the processor designation information items from among the plurality of processors, is determined according to a position at which each of the processors, excluding the damaged processor, is connected to the bus,
• wherein each of the subset of processors carries out, based on an application program including a plurality of predetermined processes each associated with any of the processor designation information items, and the table produced, the predetermined process associated with the processer designation information item designating that processor.

A multiprocessor system, comprising:

• a plurality of processing modules, including a predetermined number, being three or more, of processors,
• a bus for relaying data transmission among the respective processing modules,
• a plurality of data transmission paths within the bus, such that the predetermined number of processors carry out data transmission with respect to a predetermined processing module among the plurality of processing modules, respectively, using any of the plurality of data transmission paths,
• damaged processor specifying means for specifying at least one damaged processor among the predetermined number of processors;
• and
• communication restricting means for restricting data transmission via the bus by at least one of the processors connected to the bus at a position determined according to a position where the damaged processor is connected to the bus, the at least one processor determined as a communication restricted processor subjected to communication restriction such that the at least one processor carries out data transmission with respect to the predetermined processing module, using a data transmission path, among the plurality of data transmission paths, different from a data transmission path to be used in data transmission from the damaged processor to the predetermined processing module.

A control method for controlling a multiprocessor system having a plurality of processing modules, including a predetermined number, being three or more, of processors, and a bus for relaying data transmission among the respective processing modules, comprising:

• a step of facilitating data transmission between the predetermined number of processors and a predetermined processing module among the plurality of processing modules via one or more of a plurality of data transmission paths comprised within the bus,
• a step of specifying at least one damaged processor among the predetermined number of processors;
• and
• a step of restricting data transmission via the bus by at least one of the processors connected to the bus at a position determined according to a position where the damaged processor is connected to the bus, the at least one processor determined as a communication restricted processor subjected to communication restriction such that the at least one processor carries out data transmission with respect to the predetermined processing module, using a data transmission path, among the plurality of data transmission paths, different from a data transmission path to be used in data transmission from the damaged processor to the predetermined processing module.

A multiprocessor system, comprising:

• a plurality of processing modules, including a plurality of processors,
• a ring type bus for relaying data transmission among the respective processing modules, and
• table storage means for storing a table showing association between a subset of processors which are some of the plurality of processors and a plurality of processor designation information items each designating any of the subset of processors, in which the plurality of processor designation information items each designate any of the plurality of processors, excluding the damaged processor, as determined according to a position where at least one damaged processor is connected to the ring type bus and a processor to be designated by each of the processor designation information items from among the plurality of processors, is determined according to a position at which each of the processors, excluding the damaged processor, is connected to the bus,
• wherein each of the subset of processors carries out, based on an application program including a plurality of predetermined processes each associated with any of the processor designation information items, and the table produced, the predetermined process associated with the processer designation information item designating that processor.