Memory device including a memory block having a fixed latency data output

A method comprising:

• selecting an amount of time to delay a delayed clock signal based upon an amount of time for the read data to be output by a memory core after a read command is received at a memory block that includes the memory core;
• providing the delayed clock signal to an output clocked storage device to output read data from the memory core;
• providing a selectable version of a data clock signal to a second clocked storage device to capture the read data and causing the read data to be provided as an output of the memory block;
• selecting the data clock signal version from one of a plurality of clock edges generated by one of a plurality of clock edges of a system clock such that regardless of the an operating frequency of the system clock, the read data is provided to the output of the memory block a predetermined amount of time after the read command is received at the memory block.

A system comprising:

• a memory controller;
• a memory block coupled to the memory controller, wherein the memory block includes:
• a memory circuit including a memory core configured to output read data in response to receiving a read command;
• wherein the memory circuit is configured to provide the read data from the memory core as an output in response to being clocked by a clock signal having a selectable delay;
• wherein the delay is dependent upon a time taken for the read data to be output by the memory core after the read command is received at the memory block;
• a clock generation unit configured to capture the read data from the memory circuit and to cause the read data to be provided as an output of the memory block in response to being clocked by a selected version of a data clock signal;
• wherein the selected version of the data clock signal is selected from one of a plurality of clock edges generated by one of a plurality of clock edges of a system clock such that regardless of an operating frequency of the system clock, the read data is provided as the output of the memory block a predetermined amount of time after the read command is received at the memory block.

A memory block comprising:

• a memory circuit including:
• a memory core configured to output read data in response to receiving a read command;
• a first clocked storage device configured to capture and output the read data in response to being clocked by a clock signal;
• an adjustable delay unit configured to selectably provide the clock signal, wherein the clock signal is delayed by an amount of time that is dependent upon a time for the read data to be output by the memory core after the read command is received at the memory block;
• a clock generation unit including a second clocked storage device configured to capture the read data from the first clocked storage device and to cause the read data to be provided as an output of the memory block in response to being clocked by a version of a data clock signal;
• wherein the clock generation unit is configured to select a version of the data clock signal from one of a plurality of clock edges generated by one of a plurality of clock edges of a system clock;
• wherein the selected data clock signal version is selected such that regardless of an operating frequency of the system clock, the read data is provided to the output of the memory block a predetermined amount of time after the read command is received at the memory block.