Device having shared memory and method for transferring code data

A digital processing device, comprising:

• n processors, n being a natural number of 2 or greater, the n processors including a main processor, and n-1 application processors, wherein each of the n-1 application processors is coupled to the main processor through an independent control bus and performs an operation according to a control signal inputted through the control bus from the main processor;
• and
• a shared memory, coupled to each of the n processors through independent buses, having a boot section and at least one common section allotted, and outputting access status information related to whether a processor is accessing a common section, the boot section being for writing a boot program code to be used for booting of the n processors,
• wherein the shared memory further comprises:
• n access ports, providing an access path for each of the n processors,
• m dedicated sections, each of which is pre-allotted to be accessible by a predetermined processor only, m being a natural number of 2 or greater;
• and
• an internal controller, generating access status information related to whether a processor among the n processors is accessing the common section and outputting the generated access status information to a corresponding processor,
• wherein the main processor writes the boot program code in the common section, and then one of the n-1 application processors corresponding to the boot program code reads the boot program code from the commons section and then writes the written boot program code in the boot section.

A shared memory shared by a plurality of processors, the memory comprising:

• n access ports, providing an access path for each of the plurality of processors, n being a natural number of 2 or greater;
• m dedicated sections, each of which is pre-allotted to be accessible by a predetermined processor only, m being a natural number of 2 or greater;
• at least one common section, independently accessible and usable by the plurality of processors during a different period of time;
• a boot section, for writing a boot program code to be used for booting of at least one processor;
• and
• an internal controller, generating access status information related to whether a processor is accessing the common section and outputting the generated access status information to a corresponding processor,
• wherein the plurality of processors includes a main processor, and n-1 application processors, and each of the n-1 application processors is coupled to the main processor through an independent control bus and performs an operation according to a control signal inputted through the control bus from the main processor, and
• wherein the main processor writes the boot program code in the common section, and then one of the n-1 application processors corresponding to the boot program code reads the boot program code from the common section and then writes the written boot program code in the boot section.

A method for allowing a digital processing device to transmit a boot program code, the digital processing device having a shared memory shared by a main processor and an application processor, the method comprising:

• (a) allowing the main processor to read the boot program code from a nonvolatile memory through a first bus;
• (b) allowing the main processor to write the boot program code in a common section and to transmit a boot program code reading command to the application processor through a second bus;
• and
• (c) allowing the application processor to read the boot program code written in the common section through a third bus and to write the boot program code in a boot section,
• wherein the application processor is coupled to the main processor through an independent control bus and performs an operation according to a control signal inputted through the control bus from the main processor.