Hierarchical store buffer having segmented partitions

A method comprising:

• in a second-level store buffer having a plurality of entries included in a hierarchical microprocessor, the second-level store buffer including a segmented sequential data structure that is segmented into a plurality of partitions with one or more partitions restricted to a particular address range, a respective partition of the plurality of partitions associated with a respective definition time of a particular entry of the plurality of entries, with the particularr comprising an oldest entry of the respective partition of the plurality of partitions:
• receiving data values to be written to a memory subsystem from a plurality of execution clusters included in the hierarchical microprocessor;
• storing the received data values prior to writing the data values to the memory subsystem;
• storing a definition time reflecting a time at which a respective entry of the plurality of entries is written into;
• and
• storing a kill time reflecting another time at which another entry of the plurality of entries that has a matching same address as the respective entry is subsequently written into;
• in a plurality of first-level store buffers each operatively coupled with the second-level store buffer, each first-level store buffer being included in a respective execution cluster of the plurality of execution clusters:
• receiving data values to be written to the memory subsystem from one or more execution units of the respective execution clusters;
• and
• storing the received data values in a respective first-level store buffer prior to copying the data values to the second-level store buffer;
• copying the stored data values from the first-level store buffers to the second-level store buffer;
• comparing memory subsystem addresses of store buffer entries with a memory subsystem address of a memory load instruction;
• providing a data value from a youngest store buffer entry subsequent to scheduling of the memory load instruction;
• determining a youngest entry, for each of multiple partitions of the plurality of partitions, that matches a memory subsystem address of another memory load instruction;
• and
• excluding one or more partitions of the plurality of partitions from a determination of the youngest entry based at least partially on a load timestamp of the other memory load instruction and respective definition times associated with respective partitions of the plurality of partitions.

A microprocessor comprising:

• a plurality of execution clusters;
• a plurality of second-level architectural elements for processing instructions in the microprocessor, the plurality of second-level architectural elements being configured to act as shared resources for the plurality of execution clusters, wherein the plurality of second-level architectural elements includes a second-level store buffer that has a plurality of entries and that is configured to:
• receive data values to be written to a memory subsystem from the plurality of execution clusters;
• store the received data values prior to writing the data values to the memory subsystem;
• and
• store a definition time reflecting a time at which a respective entry of the plurality of entries is written into and a kill time reflecting another time at which another entry of the plurality of entries that has a matching same address as the respective entry is subsequently written into,
• wherein the second-level store buffer includes a segmented sequential data structure, the segmented sequential data structure segmented into a plurality of partitions with one or more partitions restricted to a particular address range, a respective partition of the plurality of partitions associated with a respective definition time of a particular entry of the plurality of entries, with the particular entry comprising an oldest entry of the respective partition of the plurality of partitions;
• and
• a plurality of first-level store buffers each operatively coupled with the second-level store buffer, each first-level store buffer being included in a respective execution cluster, the first-level store buffers each being configured to:
• receive data values to be written to the memory subsystem from one or more execution units of the respective execution cluster;
• and
• store the received data values in a respective first-level store buffer prior to copying the data values to the second-level store buffer,
• wherein the plurality of first-level store buffers and the second-level store buffer are collectively configured to:
• copy the stored data values from the first-level store buffers to the second-level store buffer;
• compare memory subsystem addresses of store buffer entries with a memory subsystem address of a memory load instruction;
• provide a data value from a youngest store buffer entry subsequent to scheduling of the memory load instruction;
• determine a youngest entry, for each of multiple partitions of the plurality of partitions, that matches a memory subsystem address of another memory load instruction;
• and
• exclude one or more partitions of the plurality of partitions from a determination of the youngest entry based at least partially on a load timestamp of the other memory load instruction and respective definition times associated with respective partitions of the plurality of partitions.

A hierarchical microprocessor including a plurality of execution clusters, the hierarchical microprocessor including:

• a second-level store buffer that includes a plurality of entries and that is configured to:
• receive data values to be written to a memory subsystem from the plurality of execution clusters;
• store the received data values prior to writing the data values to the memory subsystem;
• and
• store a definition time reflecting a time at which a respective entry of the plurality of entries is written into and a kill time reflecting another time at which another entry of the plurality of entries that has a matching same address as the respective entry is subsequently written into,
• wherein the second-level store buffer includes a segmented sequential data structure that is segmented into a plurality of partitions with one or more partitions restricted to a particular address range, a respective partition of the plurality of partitions associated with a respective definition time of a particular entry of the plurality of entries, with the particular entry comprising an oldest entry of the respective partition of the plurality of partitions;
• and
• a plurality of first-level store buffers each operatively coupled with the second-level store buffer, each first-level store buffer being included in a respective execution cluster, the first-level store buffers each being configured to:
• receive data values to be written to the memory subsystem from one or more execution units of the respective execution cluster;
• and
• store the received data values prior to copying the data values to the second-level store buffer,
• wherein the hierarchical microprocessor is configured to:
• copy the stored data values from the plurality of first-level store buffers to the second-level store buffer;
• compare memory subsystem addresses of store buffer entries with a memory subsystem address of a memory load instruction;
• provide a data value from a youngest store buffer entry subsequent to scheduling of the memory load instruction;
• determine a youngest entry, for each of multiple partitions of the plurality of partitions, that matches a memory subsystem address of another memory load instruction;
• and
• exclude one or more partitions of the plurality of partitions from a determination of the youngest entry based at least partially on a load timestamp of the other memory load instruction and respective definition times associated with respective partitions of the plurality of partitions.

A method comprising:

• in a second-level store buffer having a plurality of entries included in a hierarchical microprocessor, the second-level store buffer including a segmented sequential data structure that is segmented into a plurality of partitions with one or more partitions restricted to a particular address range:
• receiving data values to be written to a memory subsystem from a plurality of execution clusters included in the hierarchical microprocessor;
• storing the received data values prior to writing the data values to the memory subsystem;
• storing a definition time reflecting a time at which a respective entry of the plurality of entries is written into;
• and
• storing a kill time reflecting another time at which another entry of the plurality of entries that has a matching same address as the respective entry is subsequently written into,
• wherein a respective partition of the plurality of partitions is associated with a respective definition time of a particular entry of the plurality of entries, with the particular entry comprising an oldest entry of the respective partition of the plurality of partitions;
• in a plurality of first-level store buffers each operatively coupled with the second-level store buffer, each first-level store buffer being included in a respective execution cluster of the plurality of execution clusters:
• receiving data values to be written to the memory subsystem from one or more execution units of the respective execution clusters;
• and
• storing the received data values prior to copying the data values to the second-level store buffer;
• copying the stored data values from the first-level store buffers to the second-level store buffer;
• retaining first-level store buffer entries in a given first-level store buffer after the stored data values are copied to the second-level store buffer;
• comparing memory subsystem addresses of store buffer entries with a memory subsystem address of a memory load instruction;
• providing a data value from a youngest store buffer entry subsequent to scheduling of the memory load instruction;
• determining a youngest entry, for each of multiple partitions of the plurality of partitions, that matches a memory subsystem address of another memory load instruction;
• and
• excluding one or more partitions of the plurality of partitions from a determination of the youngest entry based at least partially on a load timestamp of the other memory load instruction and respective definition times associated with respective partitions of the plurality of partitions.