Instruction set architecture with instruction characteristic bit indicating a result is not of architectural importance
AssigneeInternational Business Machines Corporation
InventorsTobias Gemmeke, Markus Kaltenbach, Nicolas Maeding
Life of this patent
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Abstract
Instead of having a processor with an instruction set architecture (ISA) that includes fixed architected operands, an improved processor supports additional characteristic bits for computing instructions (e.g., a multiply-add, load/store instructions). Such additional bits for the certain instructions influence the processing of these instructions by the processor. Also, a new instruction is introduced for further usage of the proposed method. Typically these additional characteristic bits as well as the instruction can be automatically generated by compilers to provide relatively well-suited instruction sequences for the processor.
Claims12
A method, comprising:
- providing a processor;
- and
- causing the processor to execute an instruction that operates on an operand in at least one register, wherein the instruction includes at least one characteristic bit that conditionally influences the execution of the instruction by the processor in that the processor changes a number of registers in an explicit or implicit freelist that are operated on in executing the instruction with respect to a number of registers that would be operated on in executing the instruction if the at least one characteristic bit were not present, wherein the at least one characteristic bit indicates a result of an operation on the operand in the at least one register operated on by the processor when executing the instruction, wherein the indicated result of the operation on the operand in the at least one register comprises a not of architectural importance result of an intermediate type;
- wherein in response to the characteristic bit being set and a signal indicating that one of a direct bypass or forwarding is available, at least one write to a register by the processor is avoided;
- and
- wherein in response to the characteristic bit being set and the signal indicating that direct bypass and forwarding are not available, the result of the operation is written to the register.
A system for implementing a method, comprising:
- a computing network including a processing device in communication with one or more computer memory storage devices;
- and
- the computing network further configured to implement a method, the method further comprising:
- providing a processor;
- and
- causing the processor to execute an instruction that operates on an operand in at least one register, wherein the instruction includes at least one characteristic bit that conditionally influences the execution of the instruction by the processor in that the processor changes a number of registers in an explicit or implicit freelist that are operated on in executing the instruction with respect to a number of registers that would be operated on in executing the instruction if the at least one characteristic bit were not present, wherein the at least one characteristic bit indicates a result of an operation on the operand in the at least one register operated on by the processor when executing the instruction, wherein the indicated result of the operation on the operand in the at least one register comprises a not of architectural importance result of an intermediate type;
- wherein in response to the characteristic bit being set and a signal indicating that one of a direct bypass or forwarding is available, at least one write to a register by the processor is avoided;
- and
- wherein in response to the characteristic bit being set and the signal indicating that direct bypass and forwarding are not available, the result of the operation is written to the register.
Dependencies are inferred from the claim text.