Memory interface configurable for asynchronous and synchronous operation and for accessing storage from any clock domain
AssigneeCypress Semiconductor Corporation
InventorsHamid Khodabandehlou, Syed Babar Raza
Life of this patent
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Abstract
An improved memory interface circuit is provided for accessing a storage array in one of two available modes, including a synchronous mode and an asynchronous mode. The improved memory interface circuit also includes logic, which enables the storage array to reside within substantially any clock domain.
Claims18
A method for accessing a memory device that supports both synchronous and asynchronous modes of operation, and comprises a memory interface and a plurality of storage arrays, wherein at least one storage array of the plurality of storage arrays operates within a different clock domain than another storage array of the plurality of storage arrays, the method comprising:
- receiving an address of data to be accessed, and either a clock signal or an asynchronous control signal, the address being within the at least one storage array;
- latching the address when operating in the asynchronous mode, the address being latched responsive to the asynchronous control signal;
- registering the address when operating in the synchronous mode, the registered address to be supplied in synchronization with the clock signal;
- using an address multiplexer to selectively forward the latched address or the registered address, depending on the mode selected, to access the at least one storage array, access to the at least one storage array during the synchronous mode being controlled by a different clock signal than the clock signal supplied to the memory interface circuit;
- and
- generating a signal, which prevents a change that is made to the data while the data is being accessed from propagating out of the memory device while the data is being accessed.
A memory device comprising:
- a plurality of storage arrays;
- and
- a memory interface circuit configured to:
- operate in a select one of two available modes, including a synchronous mode and an asynchronous mode,
- receive an address of data to be accessed, the address being located within a storage array of the plurality of storage arrays, and
- receive a clock signal when operating in the synchronous mode, and an asynchronous control signal when operating in the asynchronous mode, the memory interface circuit including:
- an address interface logic comprising:
- an address latch configured to latch the address when operating in the asynchronous mode, the address being latched responsive to the asynchronous control signal,
- an address register configured to register the address when operating in the synchronous mode, the registered address to be supplied in synchronization with the clock signal, and
- an address multiplexer configured to selectively forward the latched address or the registered address, depending on the mode selected, to access the storage array, access to the storage array during the synchronous mode being controlled by a different clock signal than the clock signal supplied to the memory interface circuit.
Dependencies are inferred from the claim text.