Structure for maintaining memory data integrity in a processor integrated circuit using cache coherency protocols

A hardware description language (HDL) design structure encoded on a nontransitory machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a processor integrated circuit, wherein said HDL design structure comprises:

• a first element processed to generate a functional computer-simulated representation of a plurality of master processor cores;
• a second element processed to generate a functional computer-simulated representation of a plurality of cache memories, each cache memory being coupled to a respective master processor core;
• and
• a third element processed to generate a functional computer-simulated representation of a processor bus controller (PBC) coupled to the plurality of master processor cores, the PBC being configured to couple to a system memory indirectly via a memory controller, the PBC being further configured to couple directly to a master I/O device controller and a slave I/O device controller, wherein the PBC receives an initial command data request from a master processor core or a master I/O device, the initial command data request including a referenced address range in the system memory, and in response to the initial command data request the PBC sends a reflected command to any master processor core, system memory and I/O slave device that the PBC determines to be within the referenced address range;
• wherein in response to the reflected command, the master processor cores, system memory and slave I/O device in the referenced address range, send respective partial responses to the PBC, the PBC receiving from the slave I/O device a signal that indicates that a particular partial response is a partial response from the slave device, such that the PBC blocks, in response to the signal, the partial response of the memory controller, the master processor cores, and the master I/O device but not the particular partial response of the slave I/O device from inclusion in a combined response that the PBC sends to master processor cores, master I/O devices and system memory, thus enabling the slave I/O controller coupled to the slave I/O device to assume that the combined response of the PBC to the particular partial response of the slave I/O device is the same as the particular partial response of the slave I/O device, such that the PBC need not actually send a combined response to the slave I/O device.

A method in a computer-aided design system for generating a functional design model of a processor integrated circuit, the method comprising:

• generating a functional computer-simulated representation of a plurality of master processor cores;
• generating a functional computer-simulated representation of a plurality of cache memories, each cache memory being coupled to a respective master processor core;
• and
• generating a functional computer-simulated representation of a processor bus controller (PBC) coupled to the plurality of master processor cores, the PBC being configured to couple to a system memory indirectly via a memory controller, the PBC being further configured to couple directly to a master I/O device controller and a slave I/O device controller, wherein the PBC receives an initial command data request from a master processor core or a master I/O device, the initial command data request including a referenced address range in the system memory, and in response to the initial command data request the PBC sends a reflected command to any master processor core, system memory and I/O slave device that the PBC determines to be within the referenced address range;
• wherein in response to the reflected command, the master processor cores, system memory and slave I/O device in the referenced address range, send respective partial responses to the PBC, the PBC receiving from the slave I/O device a signal that indicates that a particular partial response is a partial response from the slave device, such that the PBC blocks, in response to the signal, the partial response of the memory controller, the master processor cores, and the master I/O device but not the particular partial response of the slave I/O device from inclusion in a combined response that the PBC sends to master processor cores, master I/O devices and system memory, thus enabling the slave I/O controller coupled to the slave I/O device to assume that the combined response of the PBC to the particular partial response of the slave I/O device is the same as the particular partial response of the slave I/O device, such that the PBC need not actually send a combined response to the slave I/O device.