Technique and apparatus for identifying cache segments for caching data to be written to main memory

A program stored on a non-transitory tangible medium for controlling a memory apparatus that caches data to be written to a main memory, the memory apparatus comprising:

• a cache memory including a plurality of cache segments, and memorizing, for each cache segment, validity data indicative of whether or not each of the sectors contained in each cache segment is a valid sector;
• and
• a cache controlling component for controlling access to the cache memory;
• and
• the program product for the cache controlling component including:
• program code for detecting, when writing a cache segment back to the main memory, areas having consecutive invalid sectors by accessing validity data corresponding to the cache segment;
• and
• program code for issuing, for each area detected, a read command to the main memory, making each area a valid sector, and writing the data in the cache segment back to the main memory, and wherein
• the validity data is a bit string in which logical values are arrayed, the logical values each indicating whether or not each sector is valid;
• and
• wherein the program code for detecting comprises:
• a bit inverting program code section inputting the validity data read from the cache memory, and inverting or not inverting each of the bits of the validity data, and outputting them;
• a bit mask program code section inputting the validity data output from the bit inverting program code section, wherein when a mask pattern is set, the bit mask program code section masks the validity data with the mask pattern, and if no mask pattern is set, the bit mask section outputs the validity data unchanged;
• and
• a priority encoder program code detecting the highest-order bit whose logical value is true from the validity data output from the bit mask program code section, outputting a bit position of the highest-order bit, and,
• a controller for, every time a bit position is input from the priority encoder, changing the setting of the bit inverting section, and setting a mask pattern to the bit mask section, the mask pattern masking the bit string from the highest-order bit to the input bit position, and detecting the bit positions output from the priority encoder in sequence as boundaries between areas having consecutive invalid sectors and valid sectors.

A memory apparatus that caches data to be written to a main memory, the memory apparatus comprising:

• a cache memory including a plurality of cache segments, and having a cache memory component for memorizing, for each cache segment, validity data indicative of whether or not each sector contained in each cache segment is a valid sector inclusive of valid data;
• and
• a cache controlling component for controlling access to the cache memory, wherein
• the cache controlling component includes:
• a detecting component for detecting, when writing a cache segment back to the main memory, areas having consecutive invalid sectors by accessing validity data corresponding to the cache segment;
• and a write-back controlling component issuing a read command to the main memory, the read command being for reading data to each area detected, making the area a valid sector, and writing the data in the cache segment back to the main memory, wherein
• the validity data is a bit string in which logical values are arrayed, the logical values each indicating whether or not each sector is valid;
• and
• the detecting component includes:
• a bit inverting section inputting the validity data read from the cache memory, and inverting or not inverting each of the bits of the validity data, and outputting them;
• a bit mask section inputting the validity data output from the bit inverting section, wherein when a mask pattern is set, the bit mask section masks the validity data with the mask pattern, and if no mask pattern is set, the bit mask section outputs the validity data unchanged;
• and
• a priority encoder detecting the highest-order bit whose logical value is true from the validity data output from the bit mask section, and outputting a bit position of the highest-order bit;
• and
• a controller, every time a bit position is input from the priority encoder, changing the setting of the bit inverting section, and setting a mask pattern to the bit mask section, the mask pattern masking the bit string from the highest-order bit to the input bit position;
• and
• the detecting component detecting the bit positions output from the priority encoder in sequence as boundaries between areas having consecutive invalid sectors and valid sectors.