Cache memory control method and cache memory apparatus
AssigneeFujitsu Semiconductor Limited
InventorMitsuaki Hino
Life of this patent
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Abstract
The present invention is contrived to divide an address for accessing cache memory into a first through a fourth fields from the uppermost bit side, use the first and third fields for respectively storing tag addresses, divide the second and fourth fields into one or more subfields, respectively, use one or more subfields for storing index addresses, and use the remaining subfields for respectively storing line addresses. The second field is handled as one subfield, for example, for storing an index address, and the fourth field is divided into two subfields for storing an index address in one and a line address in the other. Such a configuration manages a form of a block of which data is stored in one entry.
Claims10
A cache memory control method used for controlling an access to cache memory comprising, for each entry, a data part for storing data and a tag part for storing a tag address which is for indexing the data, comprising:
- dividing an address for accessing the cache memory into a first field through a fourth field from an uppermost bit side, the accessing being performed for each entry in units of block data having 2c lines×2f pixels in the cache memory, wherein c and f are integers and are changed dynamically according to a signal sent from a processor core which corresponds to content of image processing;
- using the first and third fields for storing tag addresses;
- dividing the second field into a first subfield for storing an index address and a second subfield for storing a line address, the second subfield having c bits;
- and
- dividing the fourth field into a third subfield for storing an index address and a fourth subfield for storing a line address, the fourth subfield having f bits,
- wherein dividing an address for accessing the cache memory includes compounding unselected bits for an index address in the second and fourth fields as bits for a line address and the compounded result is to be output to a data selector.
A cache memory control method used for controlling an access to cache memory comprising, for each entry, a data part for storing data and a tag part for storing a tag address which is for indexing the data, comprising:
- dividing an address for accessing the cache memory into a first through sixth fields from the uppermost bit side, the accessing being performed for each entry in units of block data having 2c lines×2f pixels in the cache memory, wherein c and f are integers and are changed dynamically according to a signal sent from a processor core which corresponds to content of image processing;
- using the first and fourth fields for storing tag addresses;
- using the second and fifth fields for storing index addresses;
- and
- using the third and sixth fields for storing line addresses,
- wherein the third field has c bits and the sixth field has f bits, and
- wherein dividing an address for accessing the cache memory includes compounding unselected bits for an index address in the second, third, fifth and sixth fields as bits for a line address and the compounded result is to be output to a data selector.
A cache memory apparatus accessing cache memory comprising, for each entry, a data part for storing data and a tag part for storing a tag address which is for indexing the data, comprising:
- a first extraction unit configured to extract stored tag addresses in an address specified for accessing the cache memory, the address being divided into a first through a fourth fields from the uppermost bit side, and compounding unselected bits for an index address in the second and fourth fields as bits for a line address, wherein the compounded result is to be output to a data selector, the tag addresses being stored in the first field and the third field, the accessing being performed for each entry in units of block data having 2c lines×2f pixels in the cache memory, wherein c and f are integers and are changed dynamically according to a signal sent from a processor core which corresponds to content of image processing;
- and
- a second extraction unit configured to extract index addresses stored in a first subfield and a third subfield, and line addresses stored in the second subfield having c bits and the fourth subfield having f bits, the first subfield and the second subfield constituting the second field, the third subfield and the fourth subfield constituting the fourth field.
A cache memory apparatus accessing cache memory comprising, for each entry, a data part for storing data and a tag part for storing a tag address which is for indexing the data, comprising:
- a first extraction unit configured to extract tag addresses, an address specified for accessing the cache memory, the address being divided into a first through a sixth fields from the uppermost bit side, and compounding unselected bits for an index address in the second, third, fifth and sixth fields as bits for a line address, wherein the compounded result is to be output to a data selector, the tag addresses being stored in the first field and the fourth field, the accessing being performed for each entry in units of block data having 2c lines×2f pixels in the cache memory, wherein c and f are integers and are changed dynamically according to a signal sent from a processor core which corresponds to content of image processing;
- a second extraction unit configured to extract index addresses stored in the second field and the fifth field;
- and
- a third extraction unit configured to extract line addresses stored in the third field having c bits and the sixth field having f bits.
Dependencies are inferred from the claim text.