Flash memory interface

A flash memory-interface system for storing and providing access to data mapped as a portion of main memory of a computer, the system comprising:

• a peripheral interface bus;
• a flash memory circuit configured to connect to and communicate via the peripheral interface bus and to provide the data in the flash memory mapped as a portion of main memory;
• a first in, first out FIFO buffer coupled to receive and store data from the flash memory circuit and to provide access to the stored data;
• and
• an interface circuit configured to
• communicate with the flash memory circuit via the peripheral interface bus,
• initialize the flash memory circuit for providing data to the FIFO buffer as a portion of the main memory,
• in response to a request for data starting at an address in said portion of main memory and having at least a portion thereof stored in the FIFO buffer, control the FIFO buffer to provide access to the stored data and control the flash memory circuit to provide additional data from subsequent addresses in the flash memory circuit to the FIFO buffer, and
• in response to a request for data starting at an address in a portion of main memory and not stored in the FIFO buffer, control the flash memory circuit and FIFO to provide the requested data to the FIFO buffer and, thereafter, to provide additional data from subsequent addresses in the flash memory circuit to the FIFO buffer.

A method for interfacing between a computer processor and a flash memory circuit communicatively connected to an interface circuit by a peripheral interface bus, for storing and providing access to data that is stored on the flash memory circuit and mapped as a portion of main processor memory, the method comprising:

• initializing the flash memory circuit, via the peripheral interface bus, for providing data to a first-in, first-out (FIFO) buffer coupled to receive and store data from the flash memory circuit and to provide read access to the stored data as a portion of the main memory;
• in response to a request for data mapped in said portion of main memory and having at least a portion thereof stored in the FIFO buffer, controlling the FIFO buffer to provide access to the stored data and controlling the flash memory circuit via the peripheral interface bus to provide additional data from sequential addresses in the flash memory circuit to the FIFO buffer;
• and
• in response to a request for the data mapped as a portion of main memory that is not stored in the FIFO buffer, controlling the flash memory circuit via the peripheral interface bus to provide the requested data to the FIFO buffer.