Multi-level striping and truncation channel-equalization for flash-memory system

A three-level flash device comprising:

• a high-level smart storage switch which comprises:
• an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address;
• a smart storage transaction manager that manages transactions from the host;
• a virtual storage processor that maps the host address to an assigned flash channel to generate a logical block address (LBA), the virtual storage processor performing a high level of mapping;
• a high-level striping mapper, coupled to the virtual storage processor, that stores a stripe capacity, which is the size of data that is accessible in parallel, and a scattered capacity, which is the size of data that cannot be accessed in parallel, for each flash channel, wherein the stripe capacity for all flash channels has a same value, wherein the scattered capacity varies among the flash channels;
• a virtual storage bridge between the smart storage transaction manager and a LBA bus;
• a second-level smart storage switch which comprises:
• a second upstream interface to the high-level smart storage switch for receiving commands to access NVM and for receiving data and an address from the high-level smart storage switch;
• a second-level smart storage transaction manager that manages transactions from NVM devices;
• a channel storage processor that maps the address from the high-level smart storage switch to an assigned flash channel to generate a local logical block address (LBA), the channel storage processor performing a mapping to multiple NVM devices attached to the second-level smart storage switch;
• a second-level mapper, coupled to the channel storage processor, that stores capacities of all NVM devices for each flash channel;
• a plurality of NVM controllers, each NVM controller coupled to the LBA bus to receive the LBA generated by the channel storage processor and the data from the second-level smart storage switch;
• a low-level mapper, in the NVM controller, that maps the LBA to a physical block address (PBA), the low-level mapper generating the PBA for block-mapped host data, and the low-level mapper generating the PBA and a page number for host data that is page-mapped;
• a plurality of flash channels that include the assigned flash channel, wherein a flash channel comprises:
• NVM flash memory, coupled to the NVM controller, for storing the host data at a block location identified by the PBA generated by the low-level mapper in the NVM controller, and at a page location identified by the page number for the page-mapped host data;
• wherein the second-level smart storage switch accesses the plurality of flash channels as a stripe of multiple simultaneous accesses of the plurality of flash channel for data stored in the stripe capacity;
• wherein the second-level smart storage switch accesses the plurality of flash channels as a single-channel access of one flash channel at a time for data stored in the scattered capacity;
• whereby the scattered data is accessed as single-channel access while the striped data is accessed using multiple simultaneous accesses.

A smart storage switch two-level controller comprising:

• a smart storage switch which comprises:
• an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address;
• a smart storage transaction manager that manages transactions from the host;
• a virtual storage processor that maps the host address to an assigned flash channel to generate a logical block address (LBA), the virtual storage processor performing a high level of mapping;
• a first-level striping mapper, coupled to the virtual storage processor, that stores a stripe capacity, which is the size of data that is accessible in parallel, and a scattered capacity, which is the size of data that cannot be accessed in parallel, for each flash channel, wherein the stripe capacity for all flash channels has a same value, wherein the scattered capacity varies among the flash channels;
• a virtual storage bridge between the smart storage transaction manager and a NVM controller through a LBA bus;
• a volatile memory buffer for temporarily storing host data in a volatile memory that loses data when power is disconnected;
• a NVM controller, coupled to the LBA bus to receive the LBA generated by the virtual storage processor and the host data from the virtual storage bridge;
• a low-level volatile memory buffer, coupled to the NVM controller, for buffering data;
• and
• a low-level mapper, in the NVM controller, that maps the LBA to a physical block address (PBA), the low-level mapper generating the PBA for block-mapped host data, and the low-level mapper generating the PBA and a page number for host data that is page-mapped.

A smart storage switch three-level controller comprising:

• a first-level smart storage switch which comprises:
• an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address;
• a smart storage transaction manager that manages transactions from the host;
• a virtual storage processor that maps the host address to an assigned flash channel to generate a logical block address (LBA), the virtual storage processor performing a high level of mapping;
• a first-level striping mapper, coupled to the virtual storage processor, that stores a stripe capacity, which is the size of data that is accessible in parallel, and a scattered capacity, which is the size of data that cannot be accessed in parallel, for each flash channel, wherein the stripe capacity for all flash channels has a same value, wherein the scattered capacity varies among the flash channels;
• a virtual storage bridge between the smart storage transaction manager and a LBA bus;
• a volatile memory buffer for temporarily storing host data in a volatile memory that loses data when power is disconnected;
• a second-level smart storage switch which comprises:
• a second upstream interface to the first-level smart storage switch for receiving commands to access NVM and for receiving data and an address from the first-level smart storage switch;
• a second-level smart storage transaction manager that manages transactions from the NVM devices;
• a second-level stripping mapper, coupled to the channel storage processor, that stores capacities of all NVM devices for each flash channel;
• a channel storage processor that maps the address from the first-level smart storage switch to an assigned flash channel to generate a local logical block address (LBA), the channel storage processor performing a mapping to multiple NVM devices attached to the second-level smart storage switch;
• a NVM controller, coupled to the LBA bus to receive the LBA generated by the channel storage processor and the data from the second-level smart storage switch;
• a low-level volatile memory buffer, coupled to the NVM controller, for buffering data;
• and
• a low-level mapper, in the NVM controller, that maps the LBA to a physical block address (PBA), the low-level mapper generating the PBA for block-mapped host data, and the low-level mapper generating the PBA and a page number for host data that is page-mapped.

A smart storage switch three-level controller comprising:

• a first-level smart storage switch which comprises:
• an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address;
• a smart storage transaction manager that manages transactions from the host;
• a virtual storage processor that maps the host address to an assigned flash channel to generate a logical block address (LBA), the virtual storage processor performing a high level of mapping;
• a first-level striping mapper, coupled to the virtual storage processor, that stores a stripe capacity, which is the size of data that is accessible in parallel, and a scattered capacity, which is the size of data that cannot be accessed in parallel, for each flash channel, wherein the stripe capacity for all flash channels has a same value, wherein the scattered capacity varies among the flash channels;
• a virtual storage bridge between the smart storage transaction manager and a LBA bus;
• a second-level smart storage switch which comprises:
• a second upstream interface to the first-level smart storage switch for receiving commands to access NVM and for receiving data and an address from the first-level smart storage switch;
• a second-level smart storage transaction manager that manages transactions from the NVM devices;
• a second-level stripping mapper, coupled to the channel storage processor, that stores capacities of all NVM devices for each flash channel;
• a channel storage processor that maps the address from the first-level smart storage switch to an assigned flash channel to generate a local logical block address (LBA), the channel storage processor performing a mapping to multiple NVM devices attached to the second-level smart storage switch.