I2C-bus interface with parallel operational mode
AssigneeNXP B.V.
InventorSandeep Agrawal
Life of this patent
Estimating the term…
Abstract
An electronic circuit has an interface for an I2C-bus. The interface comprises a first node for a clock line of the I2C-bus; a second node for a data line of the I2C-bus; and an I2C-bus controller for controlling an operation of the interface under combined control of the clock line and the data line. The circuit has a plurality of further nodes for connecting to a plurality of further data lines. The controller has an operational mode for control of receiving from the further nodes, or for control of supplying to the further nodes, a plurality of data bits in parallel under combined control of the clock line and the data line.
Claims13
An electronic circuit with an interface for an I2C-bus, wherein the interface comprises:
- a first node for a clock line of the I2C-bus;
- a second node for a data line of the I2C-bus;
- an I2C-bus controller for controlling an operation of the interface under combined control of the clock line and the data line;
- and
- a plurality of further nodes for connecting to a plurality of further data lines;
- and wherein the controller has an operational mode for control of receiving from the further nodes, or for control of supplying to the further nodes, a plurality of data bits in parallel under combined control of the clock line and the data line.
Software stored on a non-transitory computer-readable medium in an I2C-bus controller in an electronic circuit with an interface for an I2C-bus, wherein
- the interface comprises a first node for a clock line of the I2C-bus, a second node for a data line of the I2C-bus, and a plurality of further nodes for connecting to a plurality of further data lines;
- the I2C-bus controller is operative to control an operation of the interface under combined control of the clock line and the data line;
- and
- the software has instructions for control of receiving from the further nodes, or for control of supplying to the further nodes, a plurality of data bits in parallel under combined control of the clock line and the data line.
Dependencies are inferred from the claim text.