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US 8,266,347 B2Granted
Data transmission method and transmission circuit thereof
AssigneeHTC Corporation
InventorsShih-Hung Chu, Hsun-Hsin Chuang, Yu-Chun Peng
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Abstract
A data transmission method and the transmission circuit thereof for transmitting data between a host and a peripheral apparatus are disclosed. The data transmission method includes the following steps. First, a clock signal is transmitted by a first pin. Then, a data signal is transmitted by a second pin according to the timing of the clock signal.
Claims14
A data transmission method, comprising:
- transmitting a clock signal by a first pin, wherein the clock signal has a clock reset pulse and a plurality of clocks subsequent to the clock reset pulse;
- and
- transmitting a data signal by a second pin according to the timing of the clock signal, wherein the data signal comprises a data block for transmitting data between a host and a peripheral apparatus;
- wherein during a period of the clock reset pulse occurring in the clock signal, the data signal produces a data reset pulse within the period of the clock reset pulse, wherein a rising edge of the data reset pulse is after a rising edge of the clock reset pulse, and a falling edge of the data reset pulse is before a falling edge of the clock reset pulse;
- wherein the data reset pulse is the only one pulse produced by the data signal within the period of the clock reset pulse, and the data signal is reset after the data reset pulse and the clock reset pulse occur;
- wherein the data signal further comprises a start block between the data reset pulse and the address block, and the host is further used for transmitting a start data to the peripheral apparatus in the start block.
3 more elements
A data transmission circuit, at least comprising:
- a first pin, for transmitting a clock signal, wherein the clock signal has a clock reset pulse and a plurality of clocks subsequent to the clock reset pulse;
- and
- a second pin, transmitting a data signal according to the timing of the clock signal wherein the data signal comprises a data block for transmitting data between a host and a peripheral apparatus;
- wherein during a period of the clock reset pulse occurring in the clock signal, the data signal produces a data reset pulse within the period of the clock reset pulse, wherein a rising edge of the data reset pulse is after a rising edge of the clock reset pulse, and a falling edge of the data reset pulse is before a falling edge of the clock reset pulse;
- wherein the data reset pulse is the only one pulse produced by the data signal within the period of the clock reset pulse, and the data signal is reset after the data reset pulse and the clock reset pulse occur;
- wherein the data signal further comprises a start block between the data reset pulse and the address block, and the host is further used for transmitting a start data to the peripheral apparatus in the start block.
3 more elements
Dependencies are inferred from the claim text.