Data flow control within and between DMA channels
AssigneeApple Inc.
InventorsDominic Go, Mark D. Hayter, Puneet Kumar
Life of this patent
Estimating the term…
Abstract
In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.
Claims20
A direct memory access (DMA) controller comprising:
- a transmit circuit configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a descriptor data structure in memory, wherein a given DMA descriptor that describes a DMA transfer includes data that defines a source and a target of the DMA transfer, and wherein the transmit circuit is configured to generate read operations to read data from the source to be transmitted to the target responsive to the given DMA descriptor;
- a data flow control circuit coupled to the transmit circuit and configured to control processing of DMA descriptors by the transmit circuit;
- and
- one or more registers coupled to the data flow control circuit, wherein the one or more registers are configured to store a set of flags, and wherein a first control descriptor is codable to specify a first flag in the set of flags, and wherein, responsive to the first control descriptor in the descriptor data structure, the data flow control circuit is configured to update the first flag to a first value specified by the first control descriptor.
A system comprising:
- a host including a memory system;
- and
- a direct memory access (DMA) controller coupled to the host, wherein the DMA controller is configured to perform DMA transfers between sources and targets, wherein at least one of the source and target of each DMA transfer is the memory system, and wherein each DMA transfer is described in a DMA descriptor in a descriptor data structure stored in the memory system, and wherein the descriptor data structure includes one or more control descriptors that describe flow control between the DMA transfers, wherein the DMA controller comprises one or more registers configured to store a set of flags, and wherein the control descriptors describe the flow control as updates to the set of flags and dependencies for values in the set of flags, and wherein the DMA controller is configured to flow control the DMA transfers responsive to the control descriptors.
A method comprising:
- a direct memory access (DMA) controller performing DMA transfers between sources and targets, wherein at least one of the source and target for each DMA transfer is a memory system in a host to which the DMA controller is coupled, and wherein each DMA transfer is described in a DMA descriptor in a descriptor data structure stored in the memory system;
- the DMA controller reading one or more control descriptors from the descriptor data structure during performing of the DMA transfers, wherein the one or more control descriptors describe flow control between the DMA transfers, wherein the DMA controller comprises one or more registers configured to store a set of flags, and wherein the control descriptors describe the flow control as updates to the set of flags and dependencies for values in the set of flags;
- and
- the DMA controller flow controlling the DMA transfers responsive to the control descriptors.
Dependencies are inferred from the claim text.