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US 8,265,917 B1Granted
Co-simulation synchronization interface for IC modeling
AssigneeXilinx, Inc.
InventorsJingzhao Ou, Shay Ping Seng
Life of this patent
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Abstract
A high-level integrated circuit (“IC”) modeling system (400) includes a first co-simulator (418) modeling a first portion of an IC system and a second co-simulator (419) modeling a second portion of the IC system, each co-simulator operating according to initial simulation operating conditions (426). A co-simulation synchronization interface (424) is configured to automatically change at least one of the initial simulation operating conditions to a triggered operating condition (428) in response to a user-selected triggering signal.
Claims11
A high-level integrated circuit (“IC”) modeling system comprising:
- a first co-simulator modeling a first portion of an IC system at a first free running clock speed;
- wherein the first co-simulator executes on a host computer;
- a second co-simulator modeling a second portion of the IC system according to a second free running clock speed;
- wherein the second co-simulator emulates the second portion of the IC system on a programmable integrated circuit (IC);
- a shared first-in-first-out (“FIFO”) buffer, a first portion of the shared FIFO buffer being configured in the programmable IC and a second portion of the shared FIFO buffer being configured in the host computer;
- a co-simulation synchronization interface configured to automatically change at least one of the first free running clock speed and the second free running clock speed to a single-step mode in response to a user-selected trigger condition;
- wherein the co-simulation synchronization interface includes an interface for user specification of names of one or more signals of the IC system, of the trigger condition based on the names of the one or more signals and one or more logical operators, and of a duration that is a selected number of clock cycles and associated with the trigger condition;
- and
- wherein the co-simulation synchronization interface is further configured to return at least one of the first co-simulator or the second co-simulator from the single-step mode to the first free running clock speed or to the second free running clock speed, respectively, in response to operating in the single-step mode for the selected number of clock cycles.
6 more elements
A method of simulating an IC system comprising:
- providing a co-simulation synchronization interface configured to control a first free running clock speed of a first co-simulator of a high-level IC system modeling environment and a second free running clock speed of a second co-simulator of the high-level IC system modeling environment;
- executing the first co-simulator on a host computer, and executing the second co-simulator on a programmable integrated circuit (IC);
- wherein the co-simulation synchronization interface includes an interface for user specification of names of one or more signals of the IC system, of a trigger condition based on the names of one or more signals and one or more logical operators, and of a duration that is a selected number of clock cycles and associated with the trigger condition;
- modeling a first portion of the IC system on the first co-simulator at the first free running clock speed while concurrently modeling a second portion of the IC system on the second co-simulator at the second free running clock speed;
- sending profiling data from the first co-simulator to a first portion of a shared first-in-first-out (“FIFO”) buffer configured in the programmable IC, and moving the profiling data from the first portion of the shared FIFO buffer to a second portion of the shared FIFO buffer that is configured in the host computer;
- providing a trigger signal to the co-simulation synchronization interface in response to the one or more signals satisfying the trigger condition to automatically change the first free running clock speed and the second free running clock speed to a single-step mode for the user specified duration;
- wherein the trigger signal is provided to the co-simulation synchronization interface while modeling the first and second portions of the IC system;
- and
- automatically returning the first co-simulator to the first free running clock speed and the second co-simulator to the second free running clock speed in response to operating in the single-step mode for the selected number of clock cycles.
6 more elements
Dependencies are inferred from the claim text.