US 8,265,201 B1 · Adaptive timing using clock recovery

Abstract

Circuits and methods are provided for adjusting a frequency of a local clock signal in approximating a frequency of a host clock signal. A phase locked loop generates a local clock signal having a first phase and a first frequency. An offset adjustment circuit receives timing information relating the local clock signal to an incoming data signal and calculates a phase offset and a frequency offset indicative of adjustments to be made to the local clock signal. A first phase interpolator generates a receive clock signal from the local clock signal, the receive clock signal having a second phase and a second frequency responsive to the phase and frequency offsets. A second phase interpolator generates a transmit clock signal from the local clock signal having a third frequency responsive to the frequency offset.

Claims21

Dependent claims

A method, comprising:

receiving an incoming data signal from a host device using a receive clock signal, the host device being configured to generate the incoming data signal using spread spectrum clock (SSC) modulation based on a SSC frequency;
extracting timing information from the incoming data signal;
determining offset information based on the timing information, the receive clock signal being responsive to the offset information;
detecting the SSC frequency based on tracking the offset information;
generating a transmit clock signal based on the detected SSC frequency;
and
generating, at a local device, an outgoing data signal to the host device, based on the transmit clock signal and a local data signal, such that a clock drift associated with the outgoing data signal is within a clock drift tolerance of the host device.

4 more elements

Dependencies are inferred from the claim text.

Adaptive timing using clock recovery

Life of this patent

Adaptive timing using clock recovery

Life of this patent

Abstract

Claims21