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US 8,265,195 B2Granted
Hybrid data transmission circuit
AssigneePanasonic Corporation
InventorsTsuyoshi Ebuchi, Yoshihide Komatsu
Life of this patent
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Abstract
A data transmitter having a parallel-to-serial conversion function is supplied with a clock by a PLL circuit unit. In the PLL circuit unit, a first multiphase clock supplied to a first parallel-to-serial conversion circuit is generated and output by a multiphase VCO circuit, while a second multiphase clock supplied to a second parallel-to-serial conversion circuit is generated and output by a multiphase clock generator. The multiphase clock generator generates the second multiphase clock based on the clock output from the multiphase VCO circuit.
Claims9
A hybrid data transmission circuit, comprising:
- a data transmitter having a parallel-to-serial conversion function;
- and
- a PLL (phase-locked loop) circuit unit configured to supply a clock to the data transmitter,
- wherein
- the data transmitter includes
- a first parallel-to-serial conversion circuit configured to receive a first multiphase clock, and to perform parallel-to-serial conversion based on a first conversion ratio, and
- a second parallel-to-serial conversion circuit configured to receive a second multiphase clock, and to perform parallel-to-serial conversion based on a second conversion ratio, which is different from the first conversion ratio, and
- the PLL circuit unit includes
- a multiphase VCO (voltage-controlled oscillator) circuit configured to generate and output the first multiphase clock, and
- a multiphase clock generator configured to generate and output the second multiphase clock based on a clock output from the multiphase VCO circuit.
7 more elements
Dependencies are inferred from the claim text.