US 8,264,933 B1 · Timing loop with large pull-in range

Abstract

A sync mark detector for detecting a sync mark having alternative polarities includes an input terminal receiving data bits, wherein the data bits include constant bit groups and each constant bit group includes consecutive bits of the same logic value, the first unit outputting constant bit length values that are representative of bit lengths of constant bit groups, respectively, the second unit outputting combined bit length values, wherein each combined bit length value is representative of a sum of two consecutive constant bit length values, the third unit comparing each combined bit length value to a largest previous combined bit length value to determine a largest combined bit length value, the fourth unit determining a threshold value based on the largest combined bit length value, and the fifth unit outputting a sync mark detection signal when an individual combined bit length value is larger than the threshold value.

Claims19

Dependent claims

A sync mark detector for detecting a sync mark having alternative polarities, comprising:

an input terminal configured to receive a plurality of data bits, the plurality of data bits including a plurality of constant bit groups, each constant bit group comprising a plurality of consecutive bits of a same logic value;
a first unit configured to output a plurality of constant bit length values that are representative of bit lengths of the plurality of constant bit groups, respectively;
a second unit configured to output a plurality of combined bit length values, wherein each combined bit length value is representative of a sum of two consecutive constant bit length values;
a third unit configured to compare each combined bit length value to a largest previous combined bit length value to determine a largest combined bit length value;
a fourth unit configured to determine a threshold value based on the largest combined bit length value;
and
a fifth unit configured to output a sync mark detection signal when an individual combined bit length value is larger than the threshold value.

4 more elements

A method in a system of circuitry, the circuitry operative to detect a sync mark having alternative polarities, the method comprising:

receiving a plurality of data bits including a plurality of constant bit groups, each constant bit group comprising a plurality of consecutive bits of a same logic value;
generating a plurality of constant bit length values that are representative of bit-lengths of the plurality of constant bit groups, respectively;
generating a plurality of combined bit length values, each combined bit length value being representative of a sum of two consecutive constant bit length values;
comparing each combined bit length value to a largest previous combined bit length value to determine a largest combined bit length value;
determining a threshold value based on the largest combined bit length value;
and
outputting a sync mark detection signal when an individual combined bit length value is larger than the threshold value.

4 more elements

Dependencies are inferred from the claim text.

Timing loop with large pull-in range

Life of this patent

Timing loop with large pull-in range

Life of this patent

Abstract

Claims19