Method of increasing a timing margin for writing data to a memory array

A method for writing data to a memory array operating in synchronization with a clock signal having a first transition edge, comprising steps of:

• (a) providing a data strobe signal having a second transition edge corresponding to the first transition edge of the clock signal;
• and
• (b) using the first transition edge of the clock signal to relay the data corresponding to the second transition edge of the data strobe signal if the second transition edge of the data strobe signal is coming in earlier than the first transition edge of the clock signal, wherein:
• the first transition edge of the clock signal and the second transition edge of the data strobe signal have a first timing difference in a range from −25% to 25% of one clock cycle of the clock signal;
• and
• the data is caused to be valid in a data valid window lasting a ¾ clock cycle of the clock signal.

A method for writing data to a memory, comprising steps of:

• (a) providing a clock signal having a first transition edge;
• (b) receiving a data strobe signal having a second transition edge corresponding to the first transition edge of the clock signal;
• (c) providing a first signal and a second signal;
• (d) latching the data into the first signal in response to the second transition edge of the data strobe signal;
• and
• (e) relaying the data based on the clock signal if the data strobe signal is coming in earlier than the clock signal, wherein the step (e) comprises a sub-step of latching the data of the first signal into the second signal at a first time point lagged behind the first transition edge of the clock signal by a first time interval until a second time point in response to the first transition edge of the clock signal when the second transition edge of the data strobe signal is coming in earlier than the first transition edge of the clock signal.