Method of estimating self refresh period of semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsHyung-Dong Kim, Byung-Hwan So
Life of this patent
Estimating the term…
Abstract
In a method of estimating a self refresh period of a semiconductor memory device according to an exemplary embodiment, a plurality of internal address signals are reset in response to a refresh reset signal. The plurality of internal address signals are sequentially changed synchronously with an oscillation signal. A refresh completion signal is generated based on the plurality of internal address signals. The self refresh period is detected based on the refresh reset signal and the refresh completion signal.
Claims20
A method of estimating a self refresh period of a semiconductor memory device, the method comprising:
- resetting a plurality of internal address signals in response to a refresh reset signal in a test mode;
- sequentially changing the plurality of internal address signals synchronously with an oscillation signal;
- generating a refresh completion signal based on the plurality of internal address signals;
- and
- detecting the self refresh period based on the refresh reset signal and the refresh completion signal.
A semiconductor memory device comprising:
- an oscillator configured to generate an auto refresh signal in response to a self refresh initiation signal;
- an address counter configured to reset a plurality of internal address signals in response to a refresh reset signal and configured to sequentially change the plurality of internal address signals synchronously with the auto refresh signal;
- and
- a period detector configured to generate a self refresh period signal based on the plurality of internal address signals and the refresh reset signal.
A test system comprising:
- a semiconductor memory device configured to generate an auto refresh signal in response to a self refresh initiation signal, configured to reset a plurality of internal address signals in response to a refresh reset signal, configured to sequentially change the plurality of internal address signals synchronously with the auto refresh signal and configured to generate a refresh completion signal based on the plurality of internal address signals;
- and
- a tester configured to generate the self refresh initiation signal and the refresh reset signal and configured to generate the self refresh period signal based on the refresh reset signal and the refresh completion signal.
Dependencies are inferred from the claim text.