Data sensing arrangement using first and second bit lines
AssigneeMacronix International Co., Ltd.
InventorsYung-Feng Lin, Kuen-Long Chang, Chun-Hsiung Hung
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Abstract
Over-erasure induced noise on a data line in a nonvolatile memory that couples into an adjacent data line is mitigated by using twisted data lines and differential sensing amplifiers. Noise coupled into data lines is compensated by similar noise coupled into reference data lines and cancelled in the differential sensing amplifiers.
Claims10
A memory device, comprising:
- a memory array having a plurality of bit lines;
- a plurality of sense amplifiers, each sense amplifier in the plurality having a first input for receiving a cell signal from the memory array and a second input for receiving a reference signal;
- and
- switching arrangements by which bit lines of the plurality of bit lines are selectively coupled to the first and second inputs of respective ones of the sense amplifiers in the plurality of sense amplifiers, the switching arrangements including pairs of first and second data lines coupled to the first and second inputs of corresponding sense amplifiers, and switches by which the bit lines are selectively coupled to the pairs of first and second data lines;
- and further wherein the pairs of first and second data lines are disposed in capacitive coupling relationships with other pairs of first and second data lines, and have twisted layouts which tend to balance effects of the capacitive coupling on the first and second data lines in each pair.
A method for operating a memory device including a memory array having a plurality of bit lines, and a plurality of sense amplifiers, each sense amplifier in the plurality having a first input for receiving a cell signal from the memory array and a second input for receiving a reference signal, the method comprising:
- selectively coupling a first bit line in the memory array to the first input of one of the sense amplifiers using a first data line;
- selectively coupling a second bit line of the plurality of bit lines to the second input of the sense amplifier, one of the sense amplifiers using a second data line;
- and
- sensing data of a memory cell coupled to the first bit line using the sense amplifier, wherein the first and second data lines are disposed in capacitive coupling relationships with other data lines, and have twisted layouts which tend to balance effects of the capacitive coupling on the first and second data lines.
Dependencies are inferred from the claim text.