Integrated circuit having an array supply voltage control circuit

An integrated circuit comprising:

• a memory array comprising a plurality of memory cells, a plurality of word lines and a plurality of bit line pairs, wherein the memory array is organized in rows and columns, and wherein a row comprises a word line and all of the memory cells coupled to the word line and a column comprises a bit line pair and all of the memory cells coupled to the bit line pair;
• a plurality of array supply voltage control circuits, wherein one array supply voltage control circuit is coupled to one bit line pair, and each of the plurality of array supply voltage control circuits for receiving a power supply voltage and for providing a reduced power supply voltage to memory cells of a selected column during a write operation in response to a voltage differential on the bit line pair of the selected column, wherein each of the plurality of array supply voltage control circuits comprises:
• a first transistor having a first current electrode coupled to receive the power supply voltage, a control electrode coupled to receive a logic signal based on a select signal, and a second current electrode coupled to power supply terminals of each memory cell of the selected column of memory cells;
• a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the control electrode of the first transistor, and a second current electrode;
• a third transistor having a first current electrode coupled to the second current electrode of the second transistor, a control electrode coupled to a first bit line of the bit line pair, and a second current electrode;
• and
• a fourth transistor having a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to a second bit line of the bit line pair, and a second current electrode coupled to ground.

An integrated circuit comprising:

• a memory array comprising a plurality of memory cells, a plurality of word lines and a plurality of bit line pairs, wherein the memory array is organized in rows and columns, and wherein a row comprises a word line and all of the memory cells coupled to the word line and a column comprises a bit line pair and all of the memory cells coupled to the bit line pair;
• and
• a plurality of array supply voltage control circuits, each of the plurality of array supply voltage control circuits comprising:
• a first transistor having a first current electrode coupled to receive the power supply voltage terminal, a control electrode coupled to receive a logic signal based on a select signal, and a second current electrode coupled to power supply terminals of each memory cell of the selected column of memory cells;
• a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the control electrode of the first transistor, and a second current electrode;
• a third transistor having a first current electrode coupled to the second current electrode of the second transistor, a control electrode coupled to a first bit line of the bit line pair, and a second current electrode;
• and
• a fourth transistor having a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to a second bit line of the bit line pair, and a second current electrode coupled to ground.