Semiconductor memory device capable of memorizing multivalued data
AssigneeKabushiki Kaisha Toshiba
InventorNoboru Shibata
Life of this patent
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Abstract
In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A data storage circuit is connected to the bit lines and stores write data. The data storage circuit includes at least one static latch circuit and a plurality of dynamic latch circuits when setting 2k threshold voltages (k is a natural number equal to 3 or more) in each memory cell in the memory cell array. A control circuit refreshes data by moving the data in one of the plurality of dynamic latch circuits to the static latch circuit and further moving the data in the static latch circuit to one of the plurality of dynamic latch circuits.
Claims6
A semiconductor memory device comprising:
- a memory cell array in which a plurality of memory cells connected to word lines and bit lines are arranged in a matrix;
- a first control circuit which controls the potentials of the word lines and bit lines;
- a data storage circuit which is connected to the bit lines and which includes at least one static latch circuit for storing write data and a plurality of dynamic latch circuits when setting 2k threshold voltages (k is a natural number) in each memory cell in the memory cell array;
- and
- a second control circuit which controls the position of data stored in the dynamic latch circuits by transferring input data to said plurality of dynamic latch circuits sequentially according to a command.
Dependencies are inferred from the claim text.