Erase method and non-volatile semiconductor memory
AssigneeSamsung Electronics Co., Ltd.
InventorShoichi Kawamura
Life of this patent
Estimating the term…
Abstract
An erase method for a non-volatile memory device having a defined erase unit divided into first and second inner erase units includes; applying an erase voltage to at least one of the first and second inner erase units in accordance with respective states of corresponding first and second fail flags, after applying the erase voltage to the at least one of the first and second inner erase units, performing an erase verification on the at least one of the first and second inner erase units, and updating the at least one of the first and second fail flags in accordance with erase verification results.
Claims9
A non-volatile memory device including a semiconductor substrate and comprising:
- an array of memory cells divided into a plurality of erase units, wherein each one of the plurality of erase units includes a group of memory cells arranged according to a contiguous set of word lines and capable of being erased during a single erase operation, and an erase unit among the plurality of erase units comprises a first inner erase unit arranged according to a contiguous first subset word line in the set of word lines, and a second inner erase unit arranged according to a contiguous second subset of word line in the set of word lines;
- a first well region disposed in the semiconductor substrate and containing memory cells of the first inner erase unit connected to the first subset of word lines, and a second well region disposed in the semiconductor substrate and containing memory cells of the second inner erase unit connected to the second subset of word lines,
- wherein the first and second well regions are electrically isolated within the semiconductor substrate.
A method of performing an erase operation for a non-volatile memory device including an array of memory cells divided into a plurality of erase units, wherein each one of the plurality of erase units includes memory cells arranged according to a contiguous set of word lines that is capable of being erased as a single unit during the erase operation, and consists of a first inner unit and a second inner unit having the same size, the method comprising:
- simultaneously applying an erase voltage to the first and second inner erase units by applying a first bias voltage to a first well region of a semiconductor substrate containing memory cells of the first inner erase unit connected to a first subset of the set of word lines, and a second well region of the semiconductor substrate containing memory cells of the second inner erase unit connected to a second subset of the set of word lines;
- after simultaneously applying the erase voltage to the first and second inner erase units, performing an erase verification on the first and second inner erase units;
- and thereafter,
- upon determining that the first inner erase unit has passed the erase verification, applying the erase voltage to only the second inner erase unit.
Dependencies are inferred from the claim text.