Delayed activation of selected wordlines in memory

An apparatus, comprising:

• a plurality of memory cells to couple to a word line responsive to an external read command;
• and
• a delay circuit including a table, the delay circuit operable to activate the wordline with a delay period determined according to a read level voltage magnitude associated with the plurality of memory cells, and operable to determine a delay period count based upon values stored in the table.

A method of sensing in a memory device, comprising:

• driving a control gate of an unselected memory cell to a first voltage level;
• and
• driving the control gate of a selected memory cell to a second voltage level after a delay period, wherein driving the control gate of a selected memory cell to a second voltage level after a delay period comprises selecting the delay period based upon counting up to one of three values after a read operation begins.

A method of sensing in a memory device, comprising:

• driving a control gate of an unselected memory cell to a first voltage level;
• and
• driving the control gate of a selected memory cell to a second voltage level after a delay period, wherein driving the control gate of a selected memory cell to a second voltage level after a delay period comprises selecting the delay period based upon a table having entries referenced to the second voltage level.