Sensing memory cells
AssigneeMicron Technology, Inc.
InventorSeiichi Aritome
Life of this patent
Estimating the term…
Abstract
Methods, devices, modules, and systems for operating memory cells are taught. A method for operating memory cells includes programming at least one of the memory cells to one of a number of states. Operating memory cells also includes programming at least another one of the memory cells, which is adjacent to the programmed at least one of the memory cells, to one of a different number of states. Operating memory cells also includes sensing non-erased states of the memory cells using at least one common voltage level.
Claims28
A method for operating memory cells, comprising:
- programming a first memory cell coupled to a select line to one of a first number of states;
- programming a second memory cell coupled to the select line to one of a second number of states, the second number of states being greater in number than the first number of states;
- program a third memory cell coupled to the select line to one of a third number of states;
- and
- sensing different non-erased states of the first, second, and third memory cells using a common sensing voltage.
A method for operating an array of memory cells, comprising:
- programming at least one memory cell to one of three states;
- programming at least another memory cell, located adjacent to the programmed memory cell in the array, to one of six states;
- and
- sensing different non-erased states of the memory cells using at least one common voltage level.
A method for operating an array of memory cells, comprising:
- programming at least one memory cell to one of six states;
- programming at least another memory cell, located adjacent to the programmed memory cell in the array, to one of four states;
- and
- using at least two common voltage levels to sense at least two different non-erased states of the memory cells.
A method for operating an array of memory cells, the method comprising:
- programming a first memory cell coupled to a select line to one of three states;
- programming a second memory cell coupled to the select line to one of six states;
- and
- sensing a non-erased state of the first memory cell and a different non-erased state of the second memory cell using a common sensing voltage.
A memory device comprising:
- an array of memory cells;
- and
- control circuitry coupled to the array, wherein the control circuitry is operable to:
- program a first memory cell coupled to a select line to one of a first number of states;
- program a second memory cell coupled to the select line to one of a second number of states, the second number of states being greater in number than the first number of states;
- program a third memory cell coupled to the select line to one of a third number of states;
- and
- sense different non-erased states of the first, second, and third memory cells using a common sensing voltage.
A memory device comprising:
- an array of memory cells;
- and
- control circuitry coupled to the array, wherein the control circuitry is operable to:
- program at least one memory cell to one of three states;
- program at least another memory cell, located adjacent to the programmed memory cell in the array, to one of six states;
- and
- sense different non-erased states of the memory cells using at least one common voltage level.
A memory device comprising:
- an array of memory;
- and
- control circuitry coupled to the array, wherein the control circuitry is operable to:
- program at least one memory cell to one of six states;
- program at least another memory cell, located adjacent to the programmed memory cell in the array, to one of four states;
- and
- use at least two common voltage levels to sense at least two different non-erased states of the memory cells.
A memory device comprising:
- an array of memory cells;
- and
- control circuitry coupled to the array, wherein the control circuitry is operable to:
- program a first memory cell coupled to a select line to one of three states;
- program a second memory cell coupled to the select line to one of six states;
- and
- sense a non-erased state of the first memory cell and a different non-erased state of the second memory cell using a common sensing voltage.
Dependencies are inferred from the claim text.