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US 8,264,870 B2Granted
Semiconductor memory device
AssigneeRenesas Electronics Corporation
InventorsMasanao Yamaoka, Kenichi Osada, Kazumasa Yanagisawa
Life of this patent
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Abstract
When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.
Claims3
A semiconductor integrated circuit device comprising:
- a first diffusion layer;
- a first gate adjacent to the first diffusion layer;
- a second diffusion layer adjacent to the first gate;
- a second gate adjacent to the second diffusion layer;
- a third diffusion layer adjacent to the second gate;
- a third gate adjacent to the third diffusion layer;
- and
- a fourth diffusion layer adjacent to the third gate;
- wherein a first MOSFET included in a memory cell is made up of the first diffusion layer, the first gate, and the second diffusion layer,
- wherein a second MOSFET, disposed outside the memory cell to supply a first voltage to the memory cell, is made up of the third diffusion layer, the third gate, and the fourth diffusion layer,
- wherein the memory cell is a SRAM cell comprising a latch circuit including a pair of driver MOSFETs and a load device and two transfer MOSFETs configured to access the latch circuit,
- wherein the second MOSFET is a switch for controlling a source line connected to a source electrode of the driver MOSFET and a ground potential line so that the source line and the ground potential line are connected in an operational state of the memory cells and not connected in a standby state of the memory cells,
- wherein a source potential control circuit is disposed outside the memory cell so as to be connected between the source line and the ground potential,
- wherein, in the standby state of the memory cells, a source potential is set to an intermediate potential between the ground potential and the supply potential by the source potential control circuit, and
- wherein the source potential control circuit comprises:
- an n-channel MOSFET in which a drain electrode and a gate electrode are connected to the source line and the source electrode is connected to the ground potential line;
- and
- a resistance that connects between the source line and the ground potential line.
15 more elements
Dependencies are inferred from the claim text.