Low power SRAM based content addressable memory
AssigneeLSI Corporation
InventorsRichard J. Stephani, Gordon W. Priebe
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Abstract
An apparatus comprising a memory array and a plurality of processing circuits. The memory array may be configured to store a plurality of data bits in a plurality of rows and a plurality of columns. A plurality of data words may be stored in a respective plurality of the columns. The plurality of processing circuits may each be configured to compare (i) a test bit of a plurality of bits of an input data word with (ii) a test bit of one of the plurality of columns to determine a match. The compare may occur on a first clock cycle of an input clock signal. Each of the plurality of processing circuits may be configured to power down a respective column of the memory array if the test bit of the input data word does not match the test bit of the column.
Claims19
An apparatus comprising:
- a memory array configured to store a plurality of data bits in a plurality of rows and a plurality of columns, wherein a plurality of data words are stored in a respective plurality of said columns;
- and
- a plurality of processing circuits each configured to compare (i) a test bit of a plurality of bits of an input data word with (ii) a test bit of one of said plurality of columns to determine a match, wherein (a) said compare occurs on a first clock cycle of an input clock signal and (b) each of said plurality of processing circuits is configured to power down a respective column of said memory array if said test bit of said input data word does not match said test bit of said column.
An apparatus comprising:
- means for storing a plurality of data bits in a plurality of rows and a plurality of columns, wherein a plurality of data words are stored in a respective plurality of said columns;
- and
- means for comparing (i) a test bit of a plurality of bits of an input data word with (ii) a test bit of one of said plurality of columns to determine a match, wherein said compare (a) occurs on a first clock cycle of an input clock signal and (b) powers down a respective column of a memory array if said test bit of said input data word does not match said test bit of said column.
A method for implementing a content addressable memory comprising the steps of:
- storing a plurality of data bits in a plurality of rows and a plurality of columns, wherein a plurality of data words are stored in a respective plurality of said columns;
- and
- comparing (i) a test bit of a plurality of bits of an input data word with (ii) a test bit of one of said plurality of columns to determine a match, wherein said compare (a) occurs on a first clock cycle of an input clock signal and (b) powers down a respective column of a memory array if said test bit of said input data word does not match said test bit of said column.
Dependencies are inferred from the claim text.