Device and method for limiting drain-source voltage of transformer-coupled push pull power conversion circuit

Abstract

A circuit is proposed for limiting maximum switching FET drain-source voltage (VDS) of a transformer-coupled push pull power converter with maximum DC supply voltage VIN—MAX. Maximum VDS is accentuated by leakage inductances of the push pull transformer and the power converter circuit traces. The limiting circuit bridges the drains of the switching FETs and it includes two serially connected opposing Zener diodes each having a Zener voltage Vzx. The invention is applicable to both N-channel and P-channel FETs. In a specific embodiment, Vzx is selected to be slightly ≧2*VIN—MAX with the maximum VDS clamped to about VIN—MAX+½Vzx. In another embodiment, a proposed power switching device with integrated VDS clamping includes: In another embodiment, a proposed power switching device with integrated VDS-clamping includes a switching FET; and a Zener diode having a first terminal and a second terminal, the second terminal of the Zener diode is connected to the drain terminal of the switching FET.

Dependencies are inferred from the claim text.