Current reduction in a single stage cyclic analog to digital converter with variable resolution

A cyclic redundant signed digit (RSD) analog-to-digital converter (ADC) for converting an analog input signal to a digital output signal, the RSD ADC comprising:

• an analog input terminal for receiving an analog input signal;
• an RSD stage coupled to the analog input terminal, the RSD stage comprising:
• a plurality of comparators coupled to the analog input terminal and configured to compare a residual feedback signal to a plurality of predetermined voltages;
• a logic circuit coupled to the plurality of comparators and configured to generate a first number of bits based at least upon outputs from a first set of the plurality of comparators, the logic circuit further configured to generate a second number of bits based at least upon outputs from a second set of comparators, the second set of comparators being a subset of the first set of comparators;
• a first amplifier having a first input terminal, a second input terminal, and an output terminal selectively coupled to the second node;
• a second amplifier having a first input terminal, a second input terminal, and an output terminal selectively coupled to the second node;
• and
• at least first, second, third, and fourth capacitors, each of the first, second, third, and fourth capacitors capable of being selectively coupled between the first node and the first input terminals of both of the first and second amplifiers during an analog-to-digital conversion comprising a plurality of clock cycles;
• wherein the RSD stage has a gain factor of at least four when using the first amplifier, and the RSD stage has a gain factor of at least two when using the second amplifier, wherein the first amplifier operates to amplify the residual voltage feedback signal during a first clock cycle of the plurality of clock cycles while the second amplifier is disconnected from the first node, wherein during a second clock cycle subsequent to the first clock cycle, the second amplifier operates to amplify the residual voltage feedback signal while the first amplifier is disconnected from the first node, and wherein the second amplifier operates to amplify the residual voltage feedback signal during all remaining clock cycles of the plurality of clock cycles;
• and
• a digital section coupled to the logic circuit, the digital section configured to perform a digital alignment and correction on the first number of bits and the second number of bits to generate the digital output signal.

In a cyclic redundant signed digit (RSD) analog-to-digital converter (ADC) having a multiplying digital-to-analog converter (MDAC), the MDAC using at least one amplifier during an analog-to-digital conversion cycle comprising a plurality of clock cycles, a method for converting an analog input signal to a digital output signal, the method comprising:

• receiving the analog input signal;
• comparing a residual feedback signal to a reference voltage;
• amplifying the residual feedback signal during the first clock cycle of the plurality of clock cycles using the at least one amplifier configured to have a gain factor of at least four;
• amplifying the residual feedback signal during all clock cycles of the plurality of clock cycles subsequent to the first clock cycle using the at least one amplifier configured to have a gain factor of two and further configured to reduce a current in the at least one amplifier by a factor of at least four;
• and
• generating a plurality of digital bits that are proportional to the analog input signal.