Frequency integrator with digital phase error message for phase-locked loop applications
AssigneeApplied Micro Circuits Corporation
InventorsHanan Cohen, Simon Pang
Life of this patent
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Abstract
A digital phase-locked loop (DPLL), a supporting digital frequency integrator, and a method are provided for deriving a digital phase error signal in a DPLL. A digital frequency integrator periodically accepts a digital tdcOUT message from a Time-to-Digital Converter (TDC) representing a measured ratio of a reference clock (Tref) period to a synthesizer clock (Tdco) period. Also accepted is a digital message selecting a first ratio (Nf). In response, a digital phase error (pherr) message is periodically supplied that is proportional to an error in phase between the reference clock and the (synthesizer clock*Nf).
Claims14
A digital frequency integrator comprising:
- a first input to periodically accept a digital tdcOUT message from a Time-to-Digital Converter (TDC) representing a measured ratio of a reference clock (Tref) period to a synthesizer clock (Tdco) period;
- a second input to accept a digital message selecting a first ratio (Nf);
- and,
- an output to periodically supply a digital phase error (pherr) message proportional to an error in phase between the reference clock and the (synthesizer clock*Nf).
A digital phase-locked loop (PLL) comprising:
- a successive time-to-digital converter (STDC) having an input to accept a reference clock, an input to accept a synthesizer clock from a frequency synthesizer, and an output to periodically supply a digital tdcOUT message representing a measured ratio of the reference clock (Tref) period to the synthesizer clock (Tdco) period;
- a frequency integrator having a first input to accept the tdcOUT messages, a second input to accept a digital message selecting a first ratio (Nf), and an output to periodically supply a digital phase error (pherr) message proportional to an error in phase between reference Clock and the (synthesizer clock*Nf);
- a digital loop filter having an input to accept the pherr message and an output to periodically supply a digital control message;
- and,
- a digitally controlled oscillator having an input to accept the control messages and an output to supply the synthesizer clock in response to the control messages.
In a digital phase-locked loop (PLL), a method for deriving a digital phase error signal, the method comprising:
- a digital frequency integrator periodically accepting a digital tdcOUT message from a Time-to-Digital Converter (TDC) representing a measured ratio of a reference clock (Tref) period to a synthesizer clock (Tdco) period;
- accepting a digital message selecting a first ratio (Nf);
- and,
- periodically supplying a digital phase error (pherr) message proportional to an error in phase between the reference clock and the (synthesizer clock*Nf).
Dependencies are inferred from the claim text.