Back to results
US 8,264,283 B1Granted
Single side band mixer
AssigneeScientific Components Corporation
InventorDoron Gamliel
Life of this patent
Estimating the term…
Abstract
A single side band mixer is composed of standard digital logic elements and field effect transistors, forming a pair of quadrature generators coupled with a mixer-splitter circuit. This design results in a single side band mixer with a bandwidth from DC to at least 100 MHz when realized with CMOS digital logic circuitry. This design allows the single side band mixer to bring particular improvement to circuits including frequency synthesizers, quadrature demodulators and up-converters.
Claims14
A single side band mixer comprising:
- a first quadrature generator, a second quadrature generator, and a mixer-splitter circuit;
- said first quadrature generator having an LO input and producing LO quadrature outputs;
- said LO quadrature outputs being a first LO 0 degree phase shifted signal, a second LO 0 degree phase shifted signal, a first LO 180 degree phase shifted signal, and a second LO 180 degree phase shifted signal;
- said second quadrature generator having an IF input and producing IF quadrature outputs;
- said IF quadrature outputs being a first IF 0 degree phase shifted signal, a second IF 0 degree phase shifted signal, a first IF 180 degree phase shifted signal, and a second IF 180 degree phase shifted signal;
- said mixer-splitter circuit further comprising;
- a first FET with a first FET gate terminal, a first FET drain terminal and a first FET source terminal;
- said first LO 0 degree phase shifted signal connected to said first FET gate terminal and said first IF 0 degree phase shifted signal connected to said first FET drain terminal;
- a second FET with a second FET gate terminal, a second FET drain terminal and a second FET source terminal;
- said first LO 180 degree phase shifted signal connected to said second FET gate terminal and said first IF 180 degree phase shifted signal connected to a second FET drain terminal;
- a third FET with a third FET gate terminal, a third FET drain terminal and a third FET source terminal;
- a second LO 0 degree phase shifted signal connected to said third FET gate terminal and a second IF 0 degree phase shifted signal connected to said third FET drain terminal;
- a fourth FET with a fourth FET gate terminal, a fourth FET drain terminal and a fourth FET source terminal;
- said second LO 180 degree phase shifted signal connected to said fourth FET gate terminal and said second IF 180 degree phase shifted signal connected to said FET drain terminal;
- and,
- said first, second, third and fourth FET source terminals are connected commonly and to a load resistor, whereby said mixer RF output signal is present as a voltage across said load resistor.
13 more elements
A single side band mixer comprising;
- a first inverter with an LO input and a first inverter output;
- a second inverter with an IF input and a second inverter output;
- a first T-type flip-flop having a first clock (CK) input, and a second T-type flip-flop having a second CK input, said LO input and said first inverter output connected respectively to said first and second CK inputs;
- a “1” logic signal connected respectively to said first T-type flip-flop T input and to said second T-type flip-flop T input;
- said first and second T-type flip-flop in combination producing LO quadrature outputs;
- a third T-type flip-flop having a third CK input, and a fourth T-type flip-flop having a fourth CK input, said IF input and said second inverter output connected respectively to said third and fourth CK inputs;
- said “1” logic signal connected respectively to said third T-type flip-flop T input and to said fourth T-type flip-flop T input;
- and,
- said third and fourth T-type flip-flop in combination producing IF quadrature outputs;
- a mixer-splitter circuit interconnected to said first, second, third and fourth T-type flip-flops, said mixer-splitter circuit, in turn, comprising;
- a first mixer circuit connected to said first T-type flip-flop LO quadrature outputs and said third T-type flip-flop IF quadrature outputs, producing a first RF output;
- a second mixer circuit connected to said second T-type flip-flop LO quadrature outputs and said fourth T-type flip-flop IF quadrature outputs, producing a second RF output;
- a 2 way 0 degree splitter connected to said first RF output and said second RF output and producing a mixer RF output signal proportional to a signal from the group consisting of the sum of the frequencies of said IF input and said LO input, and the difference of the frequencies of said IF input and said LO input;
- said mixer-splitter circuit further comprising;
- a first FET with a first FET gate terminal, a first FET drain terminal and a first FET source terminal;
- a first LO 0 degree phase shifted signal connected to said first FET gate terminal and a first IF 0 degree phase shifted signal connected to said first FET drain terminal;
- a second FET with a second FET gate terminal, a second FET drain terminal and a second FET source terminal;
- a first LO 180 degree phase shifted signal connected to said second FET gate terminal and a first IF 180 degree phase shifted signal connected to a second FET drain terminal;
- a third FET with a third FET gate terminal, a third FET drain terminal and a third FET source terminal;
- a second LO 0 degree phase shifted signal connected to said third FET gate terminal and a second IF 0 degree phase shifted signal connected to said third FET drain terminal;
- a fourth FET with a fourth FET gate terminal, a fourth FET drain terminal and a fourth FET source terminal;
- a second LO 180 degree phase shifted signal connected to said fourth FET gate terminal and a second IF 180 degree phase shifted signal connected to said fourth FET drain terminal;
- wherein said LO and IF signals comprise respectively said LO and IF quadrature outputs;
- and,
- said first, second, third and fourth FET source terminals are connected commonly and to a load resistor, whereby said mixer RF output signal is present as a voltage across said load resistor.
22 more elements
Dependencies are inferred from the claim text.