Non-volatile memory device and charge pump circuit for the same
AssigneeMacronix International Co., Ltd.
InventorsYung Feng Lin, Nai-Ping Kuo
Life of this patent
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Abstract
A charge pump apparatus comprises a plurality of charge pump stages. The charge pump stages each include a respective output node. Output nodes are connected to charge boosting circuitry and to precharge circuitry. The charge boosting circuit receives one or more clock signals. The precharge circuits have a first state allowing the respective pump-stage output node to fluctuate at a level above a standby wordline voltage, and a second state coupling the respective pump-stage output node to the standby wordline voltage.
Claims9
A method for operating a charge pump, comprising:
- receiving clock signals to the charge pump;
- generating an output voltage at an output terminal of the charge pump based on a source of a wordline voltage in a memory array;
- and
- using drain capacitors of the charge pump for at least partially sustaining capacitance for read operations in the memory array.
An integrated circuit device, comprising:
- a memory array;
- charge pump circuitry having an output terminal, the charge pump circuitry coupled to the memory array and operable to receive clock signals;
- precharge circuitry for controlling the charge pump circuitry and operable to generate an output voltage at the output terminal based on a source of a wordline voltage in a memory array;
- and
- drain capacitors in the charge pump operable to at least partially sustain capacitance for read operations in the memory array.
A charge pump apparatus, comprising:
- a plurality of charge pump stages, each of the plurality of charge pump stages comprising respective output nodes;
- charge pump circuitry connected to the output nodes, the charge pump circuitry operable to receive one or more clock signals;
- precharge circuitry connected to the output nodes, the precharge circuitry operable to generate an output voltage at an output terminal of the charge pump based on a source of a wordline voltage in a memory array;
- and
- drain capacitors in the charge pump circuitry operable to at least partially sustain capacitance for read operations in the memory array.
Dependencies are inferred from the claim text.