Offset-voltage calibration circuit
AssigneeElectronics and Telecommunications Research Institute
InventorsYoung Kyun Cho, Young Deuk Jeon, Jae Won Nam, Jong Kee Kwon
Life of this patent
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Abstract
Provided is an offset-voltage calibration circuit. The circuit includes a comparator configured to receive at least two comparison voltages and output a result of a comparison between the comparison voltages, an up/down counter (UDC) configured to output an up-counting or down-counting output signal in response to an output signal of the comparator, and a current digital-to-analog converter (DAC) configured to control the amount of current supplied from a node to which the comparison voltage is applied, in response to the output signal of the UDC and control the magnitude of the comparison voltage.
Claims20
An offset-voltage calibration circuit comprising:
- a comparator configured to receive at least two comparison voltages and output a result of a comparison between the comparison voltages;
- an up/down counter (UDC) configured to output an up-counting or down-counting output signal in response to an output signal of the comparator;
- and
- a current digital-to-analog converter (DAC) configured to control an amount of current supplied from a node to which each of the comparison voltages is applied, in response to an output signal of the UDC, and control a magnitude of each of the comparison voltages,
- wherein the current DAC comprises first and second current DACs, and
- wherein the first and second current DACs selectively operate in response to the output signal of the UDC.
An offset-voltage calibration circuit, comprising:
- a comparator configured to receive at least two comparison voltages and output a result of a comparison between the comparison voltages;
- an up/down counter (UDC) configured to output an up-counting or down-counting output signal in response to an output signal of the comparator;
- a current digital-to-analog converter (DAC) configured to control an amount of current supplied from a node to which each of the comparison voltages is applied, in response to an output signal of the UDC, and control a magnitude of each of the comparison voltages;
- and
- a thermometer logic (TL) disposed between the UDC and the current DAC and configured to allow a state of the current DAC to be sequentially changed in response to the output signal of the UDC.
Dependencies are inferred from the claim text.