Delay-locked loop circuit and semiconductor device including the same

#This application claims priority from Korean Patent Application No. 10-2009-0117083, filed on Nov. 30, 2009, and Korean Patent Application No. 10-2010-0033898, filed on Apr. 13, 2010, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference.

#Apparatuses consistent with the exemplary embodiments relate to a delay-locked loop (DLL) circuit, and more particularly, to a delay-locked loop (DLL) circuit that operates stably in a wide band and a semiconductor device including the DLL circuit.

#Delay-locked loop (DLL) circuits have a small delay range. Thus, it is not easy to apply specification to DLL circuits. Also, in related DLL circuits, as a power supply voltage is varied, a phase error of a semiconductor device including a DLL circuit is varied so that the DLL circuit may become unstable.

#The exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

#FIG. 1 is a block diagram of a delay-locked loop (DLL) circuit according to an exemplary embodiment;

#FIG. 2 shows an input clock and comparison clocks of the DLL circuit of FIG. 1, according to an exemplary embodiment;

#The attached drawings for illustrating exemplary embodiments are referred to in order to gain a sufficient understanding of the exemplary embodiments, the merits thereof, and the objectives accomplished by the implementation of the exemplary embodiments. However, the exemplary embodiments are not required to, and may not, accomplish any of these objectives. Hereinafter, the exemplary embodiments will be described with reference to the attached drawings. Like reference numerals in the drawings denote like elements.

#FIG. 1 is a block diagram of a delay-locked loop (DLL) circuit 100 according to an exemplary embodiment. Referring to FIG. 1, the DLL circuit 100 according to the present exemplary embodiment may be an analog delay-locked loop circuit. Also, the DLL circuit 100 according to the present exemplary embodiment may be installed at a display driver integrated circuit (IC). In particular, the DDL 100 of FIG. 1 may be installed at a liquid crystal display (LCD) driver IC.

#The DLL circuit 100 of FIG. 1 changes the phase state of an input clock INCLK supplied to the DLL circuit 100, into in-phase states of a plurality of comparison clocks CCLK by comparing the input clock INCLK with the plurality of comparison clocks CCLK in which the input clock INCLK is sequentially generated, so as to generate output clocks OUTCLK that are used in a semiconductor device (not shown) in which the DLL circuit 100 is installed. In other words, the DLL circuit 100 of FIG. 1 changes the phase state of the input clock INCLK into the in-phase states of the comparison clocks CCLK to generate the output clocks OUTCLK that are used in the semiconductor device (not shown).