Method and apparatus for the controlled delay of an input signal
AssigneeInfineon Technologies AG
InventorWerner Grollitsch
Life of this patent
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Abstract
An apparatus for the controlled delay of an input signal includes a signal input for receiving an input signal. The input signal is supplied to a delay line with a multiplicity of delay elements. Outputs of the delay elements allow respective differently delayed phase signals to be tapped off. Furthermore, a register line with a multiplicity of register elements is provided. The register elements are each associated with one of the delay elements. Each of the register elements has a reset input and a clock input. The reset inputs are coupled to the signal input. The outputs of the delay elements are each coupled to the clock input of the register element associated therewith.
Claims20
An electronic apparatus, comprising:
- a signal input configured to receive an input signal;
- a delay line configured to delay the input signal, wherein the delay line comprises at least two delay elements, the outputs of which allow differently delayed phase signals to be tapped off therefrom;
- and
- a register line, wherein the register line comprises, for at least some delay elements, a respective register element comprising a reset input and a clock input,
- wherein the reset inputs are each coupled to the signal input, and
- wherein the outputs of the at least some delay elements are respectively coupled to the clock input of the respective register elements.
A method, comprising:
- delaying an input signal with a delay locked loop, wherein the delay locked loop comprises a delay line with at least two delay elements which allow differently delayed phase signals to be tapped off therefrom;
- providing a register line, wherein the register line comprises, for at least some of the delay elements, a respective register element comprising a reset input and a clock input;
- deriving a reset signal from the input signal and supplying the reset signal to the reset inputs of the register elements;
- and
- supplying the phase signals from the delay elements to the clock input of the respective register elements.
Dependencies are inferred from the claim text.