Delay locked loop and method of driving delay locked loop
AssigneeSamsung Electronics Co., Ltd.
InventorsJae-hong Ko, Ho-Hak Rho, Paul Kim
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Abstract
Provided are a delay locked loop (DLL) having a pulse width detection circuit and a method of driving the DLL. The DLL includes a pulse width detection circuit and a delay circuit. The pulse width detection circuit receives a reference clock signal, detects a pulse width of the reference clock signal, and outputs the detection result as a pulse width detection result signal. The delay circuit receives and delays the reference clock signal, and outputs the delayed reference clock signal as an output clock signal. The delay circuit receives the pulse width detection result signal from the pulse width detection circuit, and controls a time delay in the reference clock signal in response to the pulse width detection result signal.
Claims8
A delay locked loop comprising:
- a pulse width detection circuit receiving a reference clock signal, detecting pulse width of the reference clock signal, and outputting the detection result as a pulse width detection result signal;
- and
- a delay circuit receiving and delaying the reference clock signal, and outputting the delayed reference clock signal as an output clock signal,
- wherein the delay circuit receives the pulse width detection result signal from the pulse width detection circuit, and controls a time delay in the reference clock signal in response to the pulse width detection result signal, and
- wherein the pulse width detection circuit samples the reference clock signal a plurality of times using a plurality of sampling clock signals having different time delays, and outputs at least one of the sampling results as the pulse width detection result signal.
A delay locked loop comprising:
- a pulse width detection circuit receiving a reference clock signal, detecting pulse width of the reference clock signal, and outputting the detection result as a pulse width detection result signal;
- and
- a delay circuit receiving and delaying the reference clock signal, and outputting the delayed reference clock signal as an output clock signal,
- wherein the delay circuit receives the pulse width detection result signal from the pulse width detection circuit, and controls a time delay in the reference clock signal in response to the pulse width detection result signal,
- wherein the pulse width detection circuit comprises at least one sampling unit receiving the reference clock signal and a plurality of sampling clock signals, sampling the reference clock signal according to the respective sampling clock signals, and outputting the sampling results,
- wherein the sampling clock signals received by the at least one sampling unit are obtained by delaying the reference clock signal according to different time delays, and
- wherein the pulse width detection circuit outputs at least one of the output sampling results of the at least one sampling unit as the pulse width detection result signal.
A delay locked loop comprising:
- a pulse width detection circuit receiving a reference clock signal, detecting pulse width of the reference clock signal, and outputting the detection result as a pulse width detection result signal;
- and
- a delay circuit receiving and delaying the reference clock signal, and outputting the delayed reference clock signal as an output clock signal,
- wherein the delay circuit receives the pulse width detection result signal from the pulse width detection circuit, and controls a time delay in the reference clock signal in response to the pulse width detection result signal,
- a bias circuit generating a bias signal according to process, voltage and temperature (PVT) variations, and supplying the bias signal to the pulse width detection circuit and the delay circuit.
A method of driving a delay locked loop, the method comprising:
- receiving a reference clock signal;
- detecting a pulse width of the reference clock signal, and outputting a pulse width detection result signal;
- and
- delaying the reference clock signal and outputting the delayed reference clock signal,
- wherein delaying of the reference clock signal and outputting of the delayed reference clock signal comprises receiving the pulse width detection result signal and controlling a time delay for the reference clock signal in response to the pulse width detection result signal, and
- wherein the detecting the pulse width includes sampling the reference clock signal a plurality of times using a plurality of sampling clock signals having different time delays, and wherein at least one of the sampling results is output as the pulse width detection result signal.
Dependencies are inferred from the claim text.