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US 8,264,091 B2Granted
Integrated circuit packaging system with encapsulated via and method of manufacture thereof
AssigneeSTATS ChipPAC, Ltd.
InventorsNamJu Cho, HeeJo Chi, HanGil Shin
Life of this patent
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Abstract
A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate; attaching a buffer interconnect to and over the substrate; forming an encapsulation over the substrate covering the buffer interconnect and the integrated circuit; and forming a via in the encapsulation and to the buffer interconnect.
Claims20
A method of manufacture for forming an integrated circuit packaging system comprising:
- providing a substrate;
- mounting an integrated circuit over the substrate;
- attaching a buffer interconnect to and over the substrate;
- forming an encapsulation over the substrate covering the buffer interconnect, and the integrated circuit;
- and
- forming a via in the encapsulation and to a recess of the buffer interconnect.
3 more elements
A method of manufacture for forming an integrated circuit packaging system comprising:
- providing an substrate having an substrate first side and an substrate second side;
- mounting an integrated circuit over the substrate first side;
- attaching a buffer interconnect along the peripheral portion of the substrate first side;
- forming an encapsulation over the substrate first side and covering the buffer interconnect and the integrated circuit;
- and
- forming a via through the encapsulation to a recess of the buffer interconnect with a top portion of the via coplanar with an encapsulation top side of the encapsulation.
3 more elements
An integrated circuit packaging system comprising:
- a substrate;
- an integrated circuit over the substrate;
- a buffer interconnect attached to and over the substrate;
- a via directly attached to the buffer interconnect in a recess of the buffer interconnect;
- and
- an encapsulation over the substrate covering the via, the buffer interconnect, and the integrated circuit, with a top portion of the via exposed.
3 more elements
Dependencies are inferred from the claim text.