Semiconductor devices with low resistance back-side coupling

An electronic element comprising:

• a thinned substrate comprising a semiconductor, wherein the thinned substrate had an initial thickness between an initial first surface and an opposed initial second surface prior to thinning, and the thinned substrate has a final thickness between the initial first surface and a new second surface less than the initial thickness due to removal of material from the initial second surface after thinning;
• one or more pipes or trenches previously extending into the initial substrate from the initial first surface by a distance less than the initial thickness and greater than the final thickness, wherein the pipes or trenches are filled with a conductor to form conductor filled pipes or trenches, and one or more lower faces of the conductor in the conductor filled pipes or trenches is exposed at and coplanar with the new second surface;
• a semiconductor layer over the initial first surface and the conductor filled pipes or trenches, wherein the semiconductor layer comprises a region adapted for device formation and having a new first surface;
• one or more semiconductor devices formed in the device region;
• and
• a conductor supported by the new second surface making Ohmic contact to the one or more lower faces of the conductor in the conductor filled pipes or trenches.

An electronic device comprising:

• a thinned substrate which had an initial thickness between a front surface and an initial back surface prior to thinning the substrate, and the thinned substrate has a final thickness, after thinning, between the front surface and a final back surface, wherein the final thickness is less than the initial thickness due to removal of material from the initial back surface during thinning;
• conductor filled vias previously extending, prior to thinning the substrate, substantially from the front surface part-way through the substrate to a predetermined thickness from the initial back surface, wherein one or more lower faces of the conductor filled vias is exposed at and coplanar with the final back surface;
• a semiconductor layer overlying the front surface and the conductor filled vias;
• one or more devices in the semiconductor layer;
• and
• an electrical conductor in Ohmic contact with the one or more of the conductor filled vias exposed on the final back surface.