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US 8,264,077 B2Granted
Backside metal of redistribution line with silicide layer on through-silicon via of semiconductor chips
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWen-Chih Chiou, Weng-Jin Wu
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Abstract
An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate. The TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is over the backside of the semiconductor substrate and connected to the back end of the TSV. A silicide layer is over and contacting the RDL.
Claims16
An integrated circuit structure comprising:
- a semiconductor substrate comprising a front side and a backside;
- a through-silicon via (TSV) penetrating the semiconductor substrate, the TSV comprising a back end extending to the backside of the semiconductor substrate;
- a redistribution line (RDL) over the backside of the semiconductor substrate and connected to the back end of the TSV;
- a silicide layer over and adjoining the RDL;
- an active circuit on the front side of the semiconductor substrate, wherein the active circuit and the RDL are on opposite sides of the semiconductor substrate;
- a passivation layer over the RDL;
- and
- an opening in the passivation layer, and directly over a portion of the RDL, wherein the opening penetrates through the silicide layer, and wherein the portion of the RDL is exposed through the opening.
5 more elements
An integrated circuit structure comprising:
- a semiconductor substrate comprising a front side and a backside;
- a through-silicon via (TSV) penetrating the semiconductor substrate, the TSV comprising a back end extending beyond the backside of the semiconductor substrate;
- a redistribution line (RDL) over the backside of the semiconductor substrate and connected to the back end of the TSV, wherein the RDL comprises copper;
- a silicide layer over and adjoining the RDL, wherein the silicide layer comprises copper silicide;
- a passivation layer over and adjoining the RDL;
- an opening in the passivation layer and the silicide layer, wherein a portion of the RDL is exposed through the opening;
- a metal finish in the opening and contacting the RDL;
- and
- an active circuit on the front side of the semiconductor substrate, wherein the active circuit and the RDL are on opposite sides of the semiconductor substrate.
6 more elements
Dependencies are inferred from the claim text.