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US 8,264,066 B2Granted
Liner formation in 3DIC structures
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChing-Yu Lo, Hung-Jung Tu, Hai-Ching Chen, Tien-I Bao, Wen-Chih Chiou, Chen-Hua Yu
Life of this patent
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Abstract
An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner.
Claims13
An integrated circuit structure comprising:
- a semiconductor substrate comprising a through-semiconductor via (TSV) opening extending into the semiconductor substrate;
- and
- a dielectric liner in the TSV opening, wherein the dielectric liner comprises a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening, wherein a top surface of the bottom portion of the dielectric liner is rounded, with a radius greater than about 20 percent of a bottom width of the TSV opening, and wherein the bottom portion of the dielectric liner has a height greater than a thickness of the sidewall portion of the dielectric liner.
An integrated circuit structure comprising:
- a substrate comprising an opening extending into the substrate, wherein the opening has an aspect ratio greater than about 6;
- and
- a dielectric liner in the opening, wherein the dielectric liner comprises a sidewall portion on a sidewall of the opening and a bottom portion on a bottom of the opening, and wherein all thicknesses of the sidewall portion are no greater than a height of the bottom portion.
Dependencies are inferred from the claim text.