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US 8,264,061 B2Granted
Phase change memory cell and devices containing same
AssigneeRound Rock Research, LLC
InventorRussell C. Zahorik
Life of this patent
Estimating the term…
Abstract
A device with a memory array is disclosed. In one embodiment, the memory array includes a plurality of memory cells, each including an electrode and a phase change material. The electrode may be disposed on a substrate, the electrode having a sublithographic lateral dimension parallel to the substrate. The phase change material may be coupled to the electrode and include a lateral dimension parallel to the substrate and greater than the sublithographic lateral dimension of the electrode.
Claims26
A memory device comprising:
- an array of chalcogenide memory cells;
- a conductive substrate comprising an X-Y grid of electrodes on which the array of chalcogenide memory cells are formed;
- each memory cell comprising;
- a) a lower electrode formed in a window formed in a layer of insulating material, wherein the lower electrode material of the chalcogenide memory cells is selected from the group consisting of Ti, TiN, and TiCxNy, the window having insulator spacers formed therein defining a dimension of the memory cell lower electrode;
- b) a chalcogenide material formed over the lower electrode;
- and c) an upper electrode formed over the chalcogenide material and an insulator formed over the memory cell;
- the upper electrode in electrical contact with an upper X-Y grid of conductors;
- diodes in series with the chalcogenide memory cells;
- wherein the upper and lower X-Y grid of conductors are configured for addressing the memory cells;
- and
- wherein the diodes provide for read/write operations of the memory cells.
8 more elements
A memory array device comprising:
- an array of chalcogenide memory cells;
- a conductive substrate comprising an X-Y grid of electrodes on which the array of chalcogenide memory cells are formed;
- each memory cell comprising:
- a) a first electrode within a pore of a dielectric layer, wherein the first electrode comprises material selected from the group consisting of Ti, TiN, and TiCxNy, the dielectric layer formed over the X-Y grid of electrodes and the pore extending from an upper surface of the dielectric layer to a lower surface of the dielectric layer adjacent the conductive substrate, the first electrode having an outer surface that is substantially circular and having an exposed first surface having a sublithographic dimension in a first direction parallel to the exposed first surface, the first electrode also having a second surface opposite the first surface and adjacent the conductive substrate, the second surface having a sublithographic dimension in an additional direction parallel to the second surface;
- and b) a layer of phase change material coupled to the exposed first surface of the first electrode.
2 more elements
A memory array device comprising:
- an array of chalcogenide memory cells;
- a conductive substrate comprising an X-Y grid of electrodes on which the array of chalcogenide memory cells are formed;
- each memory cell comprising:
- a) a first electrode within a pore of a dielectric layer, wherein the first electrode comprises material selected from the group consisting of Ti, TiN, and TiCxNy, the dielectric layer formed over the X-Y grid of electrodes and the pore extending from an upper surface of the dielectric layer to a lower surface of the dielectric layer adjacent the conductive substrate, the first electrode having an outer surface that is generally rectangular and having an exposed first surface having a sublithographic dimension in a first direction parallel to the exposed first surface, the first electrode also having a second surface opposite the first surface and adjacent the conductive substrate, the second surface having a sublithographic dimension in an additional direction parallel to the second surface;
- and b) a layer of phase change material coupled to the exposed first surface of the first electrode.
2 more elements
A device with a memory array, the memory array comprising:
- an array of chalcogenide memory cells;
- a conductive substrate comprising an X-Y grid of electrodes on which the array of chalcogenide memory cells are formed;
- each memory cell comprising:
- a) a first electrode disposed on the X-Y grid of electrodes, wherein the first electrode comprises material selected from the group consisting of Ti, TiN, and TiCxNy, the first electrode including a sublithographic lateral dimension parallel to the substrate;
- b) a phase change material coupled to the first electrode, wherein the phase change material includes a lateral dimension parallel to the substrate and greater than the sublithographic lateral dimension of the first electrode;
- and c) a second electrode disposed over the phase change material, wherein the second electrode includes a planar surface adjacent the phase change material and parallel to the substrate.
3 more elements
An electronic device comprising:
- an array of chalcogenide memory cells;
- a conductive substrate comprising an X-Y grid of electrodes on which the array of chalcogenide memory cells are formed;
- each memory cell comprising;
- a) a lower electrode formed in a window formed in a layer of insulating material, wherein the lower electrode material of the chalcogenide memory cells is selected from the group consisting of Ti, TiN, and TiCxNy, the window defining a dimension of the memory cell lower electrode, the dimension being sublithographic;
- b) a chalcogenide material formed over the lower electrode;
- and c) an upper electrode formed over the chalcogenide material and an insulator formed over the memory cell;
- the upper electrode in electrical contact with an upper X-Y grid of conductors;
- diodes in series with the chalcogenide memory cells;
- wherein the upper and lower X-Y grid of conductors are configured for addressing the memory cells;
- and
- wherein the diodes provide for read/write operations of the memory cells.
8 more elements
Dependencies are inferred from the claim text.