MOS-driver compatible JFET structure with enhanced gate source characteristics

A JFET device, comprising:

• a gate contact, a drain contact, and a source contact;
• a first gate region of semiconductor material, said first gate region having a top surface adjacent said gate contact and one or more interior surfaces;
• a second gate region of semiconductor material surrounding each of the one or more interior surfaces said first gate region so that a first p-n junction is formed between said first gate region and said second gate region such that a single p-n junction is formed between said gate contact and said second gate region;
• a channel region of semiconductor material adjacent said source contact and said second gate region so as to form a second p-n junction between said second gate region and said channel region, the first p-n junction and the second p-n junction being located between said gate contact and the channel region;
• and
• a drift region of semiconductor material disposed adjacent said drain contact, said channel region, and said second gate region so as to form a third p-n junction between said second gate region and said drift region;
• wherein said first p-n junction has a depletion width that is adjustable based at least in part on a gate voltage applied to said gate contact, said second p-n junction has a depletion width that is adjustable based at least in part on the Rate voltage, wherein when the gate voltage is greater than a threshold voltage for the first p-n junction, the depletion width of said second p-n junction decreases as the depletion width of said first p-n junction increases.

A normally off SiC JFET device, comprising:

• a gate contact, a drain contact, and a source contact;
• an n gate region of n-type semiconductor material, said n gate region having a top surface adjacent said gate contact and one or more interior surfaces;
• a p gate region of p-type semiconductor material surrounding each of the one or more interior surfaces of said n gate region, said n gate region and said p gate region forming a first p-n junction between said n gate region and said p gate region such that a single p-n junction is formed between said gate contact and said n gate region;
• an n channel region of n-type semiconductor material adjacent said source contact and said p gate region, said n channel region and said p gate region forming a second p-n junction between said n channel region and said p gate region, the first p-n junction and the second p-n junction being located between said gate contact and the n channel region;
• an n drift region of n-type semiconductor material adjacent said drain contact, said n channel region, and said p gate region, said n drift region and said p gate region forming a third p-n junction between said n drift region and said p gate region;
• wherein said first p-n junction has a depletion width that is adjustable based at least in part on a gate voltage applied to said gate contact, said second p-n junction has a depletion width that is adjustable based at least in part on the gate voltage, wherein when the Rate voltage is greater than a threshold voltage for the first p-n junction, the depletion width of said second p-n junction decreases as the depletion width of said first p-n junction increases.