US 8,264,055 B2Granted

CMOS thermoelectric refrigerator

AssigneeTexas Instruments Incorporated

InventorHenry Litzmann Edwards

Life of this patent

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Abstract

A CMOS thermoelectric refrigerator made of an NMOS transistor and PMOS transistor connected in series through a cold terminal is disclosed. Active areas of the NMOS and PMOS transistors are less than 300 nanometers wide, to reduce thermal conduction between the cold terminal and the IC substrate. Drain nodes of the NMOS and PMOS transistors are connected through hot terminals to a biasing circuit. The drain node of the NMOS transistor is biased positive with respect to the drain node of the PMOS transistor, to extract hot electrons and hot holes from the cold terminal. Biases on the drain nodes and gates of the NMOS and PMOS transistors may be adjusted to optimize the efficiency of the CMOS thermoelectric refrigerator or maximize the thermal power of the CMOS thermoelectric refrigerator. The cold terminal may be configured to cool a selected component in the IC, such as a transistor.

Claims19

Dependent claims

A complementary metal oxide semiconductor (CMOS) thermoelectric refrigerator, comprising:

an n-channel metal oxide semiconductor (NMOS) transistor, in which:
an NMOS drain region of said NMOS transistor is less than 300 nanometers wide;
an NMOS source region of said NMOS transistor is less than 300 nanometers wide;
said NMOS drain region is electrically connected to an NMOS hot terminal interconnect element of said CMOS thermoelectric refrigerator;
and said NMOS source region is electrically connected to a cold terminal of said CMOS thermoelectric refrigerator;
a p-channel metal oxide semiconductor (PMOS) transistor, in which:
PMOS drain region of said PMOS transistor is less than 300 nanometers wide;
a PMOS source region of said PMOS transistor is less than 300 nanometers wide;
said PMOS drain region is electrically connected to a PMOS hot terminal interconnect element of said CMOS thermoelectric refrigerator;
and said PMOS source region is electrically connected to said cold terminal;
and a bias circuit connected to said NMOS hot terminal interconnect element and said PMOS hot terminal interconnect element, said bias circuit configured to bias the NMOS hot terminal interconnect element positive with respect to the PMOS hot terminal interconnect element to extract hot electrons and hot holes from the cold terminal.

8 more elements

An integrated circuit, comprising:

a CMOS thermoelectric refrigerator, further comprising:
an NMOS transistor, in which:
an NMOS drain region of said NMOS transistor is less than 300 nanometers wide;
an NMOS source region of said NMOS transistor is less than 300 nanometers wide;
said NMOS drain region is electrically connected to an NMOS hot terminal interconnect element of said CMOS thermoelectric refrigerator;
and said NMOS source region is electrically connected to a cold terminal of said CMOS thermoelectric refrigerator;
a PMOS transistor, in which:
a PMOS drain region of said PMOS transistor is less than 300 nanometers wide;
a PMOS source region of said PMOS transistor is less than 300 nanometers wide;
said PMOS drain region is electrically connected to a PMOS hot terminal interconnect element of said CMOS thermoelectric refrigerator;
and said PMOS source region is electrically connected to said cold terminal;
and a bias circuit connected to said NMOS hot terminal interconnect element and said PMOS hot terminal interconnect element, said bias circuit configured to bias the NMOS hot terminal interconnect element positive with respect to the PMOS hot terminal interconnect element to extract hot electrons and hot holes from the cold terminal;
and a transistor thermally connected to said cold terminal.

10 more elements

A method of forming an integrated circuit, comprising the steps of:

forming a CMOS thermoelectric refrigerator, further comprising the steps of:
forming an NMOS transistor, further comprising the steps of:
forming an NMOS drain region of said NMOS transistor such that said NMOS drain region is less than 300 nanometers wide;
forming an NMOS source region of said NMOS transistor such that said NMOS source region is less than 300 nanometers wide;
forming an electrical connection between said NMOS drain region and an NMOS hot terminal interconnect element of said CMOS thermoelectric refrigerator;
and forming an electrical connection between said NMOS source region and a cold terminal of said CMOS thermoelectric refrigerator;
forming a PMOS transistor, further comprising the steps of:
forming a PMOS drain region of said PMOS transistor such that said PMOS drain region is less than 300 nanometers wide;
forming a PMOS source region of said PMOS transistor such that said PMOS source region is less than 300 nanometers wide;
forming an electrical connection between said PMOS drain region and a PMOS hot terminal interconnect element of said CMOS thermoelectric refrigerator;
and forming an electrical connection between said PMOS source region and said cold terminal;
and forming a bias circuit connected to said NMOS hot terminal interconnect element and said PMOS hot terminal interconnect element, said bias circuit configured to bias the NMOS hot terminal interconnect element positive with respect to the PMOS hot terminal interconnect element to extract hot electrons and hot holes from the cold terminal;
and forming a thermal connection between a transistor and said cold terminal.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/538,571Filed 10 Aug 2009 · us provisional application
Priority: 8 Aug 2008
Published: US 2010/0032748 A111 Feb 2010
Granted: 11 Sep 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 84/85
Of only insulated-gate FETs [IGFET]: complementary IGFETs, e.g. CMOS
H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 89/105
Integrated device layouts: adapted for thermal considerations