Integrated circuit including cross-coupled transistors with two transistors of different type having gate electrodes formed by common gate level feature with shared diffusion regions on opposite sides of common gate level feature

A method for creating a layout of an integrated circuit, comprising:

• operating a computer to define a gate electrode level region having a number of adjacently positioned gate electrode feature channels, each gate electrode feature channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate electrode feature channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a first line end spacing and a second end located adjacent to a second line end spacing, each gate level feature forming an electrically conductive path extending between its first and second ends,
• wherein the gate electrode level region includes a first gate level feature that forms a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type, such that the gate electrode of the first transistor of the first transistor type is electrically connected to the gate electrode of the first transistor of the second transistor type, wherein the gate electrode of the first transistor of the first transistor type is substantially co-aligned with the gate electrode of the first transistor of the second transistor type along a first common line of extent in the first direction,
• wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of only one transistor that is a second transistor of the first transistor type,
• wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of only one transistor that is a second transistor of the second transistor type,
• wherein the first gate level feature is positioned between the second and third gate level features in the second direction,
• wherein the first and second transistors of the first transistor type are collectively separated from the first and second transistors of the second transistor type by an inner portion of the gate electrode level region,
• wherein the gate electrode of the second transistor of the first transistor type is electrically connected to the gate electrode of the second transistor of the second transistor type,
• wherein the first and second transistors of the first transistor type share a first diffusion region of a first diffusion type, wherein the first diffusion region of the first diffusion type is electrically connected to a common node,
• wherein the first and second transistors of the second transistor type share a first diffusion region of a second diffusion type, wherein the first diffusion region of the second diffusion type is electrically connected to the common node, and
• wherein the first diffusion region of the first diffusion type and the first diffusion region of the second diffusion type are respectively formed at opposite sides of the first gate level feature.

A data storage device having program instructions stored thereon for generating a layout of an integrated circuit, comprising:

• program instructions for defining a gate electrode level region having a number of adjacently positioned gate electrode feature channels, each gate electrode feature channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate electrode feature channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a first line end spacing and a second end located adjacent to a second line end spacing, each gate level feature forming an electrically conductive path extending between its first and second ends,
• wherein the gate electrode level region includes a first gate level feature that forms a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type, such that the gate electrode of the first transistor of the first transistor type is electrically connected to the gate electrode of the first transistor of the second transistor type, wherein the gate electrode of the first transistor of the first transistor type is substantially co-aligned with the gate electrode of the first transistor of the second transistor type along a first common line of extent in the first direction,
• wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of only one transistor that is a second transistor of the first transistor type,
• wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of only one transistor that is a second transistor of the second transistor type,
• wherein the first gate level feature is positioned between the second and third gate level features in the second direction,
• wherein the first and second transistors of the first transistor type are collectively separated from the first and second transistors of the second transistor type by an inner portion of the gate electrode level region,
• wherein the gate electrode of the second transistor of the first transistor type is electrically connected to the gate electrode of the second transistor of the second transistor type,
• wherein the first and second transistors of the first transistor type share a first diffusion region of a first diffusion type, wherein the first diffusion region of the first diffusion type is electrically connected to a common node,
• wherein the first and second transistors of the second transistor type share a first diffusion region of a second diffusion type, wherein the first diffusion region of the second diffusion type is electrically connected to the common node, and
• wherein the first diffusion region of the first diffusion type and the first diffusion region of the second diffusion type are respectively formed at opposite sides of the first gate level feature.