An integrated circuit, comprising:
- a first transistor of a first transistor type formed in part by a first gate electrode formed to extend lengthwise in a first direction, wherein the first gate electrode corresponds to a portion of a first gate level conductive structure formed within a corresponding gate level channel within a gate level region of the integrated circuit;
- a first transistor of a second transistor type formed in part by a second gate electrode formed to extend lengthwise in the first direction, wherein the second gate electrode corresponds to a portion of a second gate level conductive structure formed within a corresponding gate level channel within the gate level region of the integrated circuit, wherein the second gate electrode is substantially co-aligned with the first gate electrode along a common line of extent in the first direction;
- a second transistor of the first transistor type formed in part by a third gate electrode formed to extend lengthwise in the first direction, wherein the third gate electrode corresponds to a portion of a third gate level conductive structure formed within a corresponding gate level channel within the gate level region of the integrated circuit;
- a second transistor of the second transistor type formed in part by a fourth gate electrode formed to extend lengthwise in the first direction, wherein the fourth gate electrode corresponds to a portion of a fourth gate level conductive structure formed within a corresponding gate level channel within the gate level region of the integrated circuit, wherein the fourth gate electrode is substantially co-aligned with the third gate electrode along a common line of extent in the first direction,
- wherein each of the first and second transistors of the first transistor type is physically separate from each of the first and second transistors of the second transistor type,
- wherein each of the first, second, third, and fourth gate level conductive structures is defined within its corresponding gate level channel without physically contacting another gate level conductive structure defined within an adjoining gate level channel,
- wherein the first and fourth gate electrodes are electrically connected to each other through one or more conductive structures located within at least one level of the integrated circuit other than the gate electrode level of the integrated circuit,
- wherein the second and third gate electrodes are electrically connected to each other through one or more conductive structures located within at least one level of the integrated circuit other than the gate electrode level of the integrated circuit,
- wherein each of the first and third gate level conductive structures are physically separated from each of the second and fourth gate level conductive structures;
- a first conductive contacting structure formed to physically connect to the first gate level conductive structure at a location between the first and second gate electrodes;
- and
- a second conductive contacting structure formed to physically connect to the third gate level conductive structure at a location between the third and fourth gate electrodes, wherein the second conductive contacting structure is offset from the first conductive contacting structure in the first direction.