Lateral power transistor and method for producing same

A lateral power transistor comprising:

• a semiconductor layer, in the semiconductor layer:
• a source zone of a first conduction type,
• a drain zone arranged at a distance from the source zone in a lateral direction of the semiconductor layer,
• a drift zone adjacent to the drain zone in the direction of the source zone, and
• a body zone of a second conduction type complementary to the first conduction type, said body zone being arranged between the drift zone and the source zone,
• an electrode layer, which is dielectrically insulated from the semiconductor layer and which forms a gate electrode in a first section and a field plate in a second section,
• wherein the gate electrode is arranged adjacent to the body zone and an accumulation section of the drift zone and is insulated from the semiconductor layer by means of a gate dielectric layer, and
• wherein the field plate is arranged adjacent to a further section of the drift zone and is insulated from the semiconductor layer by means of a field plate dielectric layer, which is thicker than the gate dielectric layer,
• wherein the gate electrode has a first gate electrode section and a second gate electrode section, the second gate electrode section being arranged between the first gate electrode section and the field plate, and
• wherein
• the field plate has an outer surface arranged at a first height level relative to a reference level in the semiconductor layer,
• the first gate electrode section has an outer surface arranged at least in sections at a second height level, which is closer to the reference level in comparison with the first height level, and
• the second gate electrode section has an outer surface extending in the lateral direction that is arranged at at least one first intermediate level arranged between the first and second height levels relative to the reference level;
• wherein the first and the second gate electrode sections are each insulated from the semiconductor layer by the gate dielectric layer that is thinner than the field plate dielectric layer such that the gate dielectric layer has a substantially uniform thickness for both the first and the second gate electrode sections;
• wherein the first height level, the second height level and the first intermediate level are defined by that side of the gate dielectric layer facing away from the semiconductor layer;
• and
• wherein the gate electrode has a third gate electrode section, which is arranged adjacent to the body zone and which is arranged at a second intermediate level.

A power transistor comprising:

• a semiconductor layer having a source zone of a first conduction type,
• a drain zone spaced apart from the source zone in a lateral direction,
• a drift zone adjacent to the drain zone in the direction of the source zone, and
• a body zone of a second conduction type complementary to the first conduction type, said body zone interposed between the drift zone and the source zone,
• an electrode layer dielectrically insulated from the semiconductor layer, the electrode layer including a gate electrode and a field plate,
• wherein the gate electrode is arranged adjacent to the body zone and a first section of the drift zone and is insulated from the semiconductor layer by means of a gate dielectric layer, and
• wherein the field plate is arranged adjacent to a further section of the drift zone and is insulated from the semiconductor layer by a field plate dielectric layer, which is thicker than the gate dielectric layer,
• wherein
• the field plate has an outer surface arranged at a first height level relative to a reference level in the semiconductor layer,
• a first gate electrode section is has an outer surface arranged at least partially at a second height level, which is closer to the reference level, and
• a second gate electrode section, laterally displaced from the first gate electrode section, having an outer surface extending in the lateral direction that is disposed at a first intermediate level arranged between the first and second height levels relative to the reference level;
• and
• wherein the first and the second gate electrode sections are each insulated from the semiconductor layer by the gate dielectric layer that is thinner than the field plate dielectric layer such that the gate dielectric layer has a substantially uniform thickness for both the first and the second gate electrode sections;
• and
• wherein the first height level, the second height level and the first intermediate level are defined by that side of the gate dielectric layer facing away from the semiconductor layer.