US 8,264,038 B2 · Buried floating layer structure for improved breakdown

Abstract

A buried layer architecture which includes a floating buried layer structure adjacent to a high voltage buried layer connected to a deep well of the same conductivity type for components in an IC is disclosed. The floating buried layer structure surrounds the high voltage buried layer and extends a depletion region of the buried layer to reduce a peak electric field at lateral edges of the buried layer. When the size and spacing of the floating buried layer structure are optimized, the well connected to the buried layer may be biased to 100 volts without breakdown. Adding a second floating buried layer structure surrounding the first floating buried layer structure allows operation of the buried layer up to 140 volts. The buried layer architecture with the floating buried layer structure may be incorporated into a DEPMOS transistor, an LDMOS transistor, a buried collector npn bipolar transistor and an isolated CMOS circuit.

Claims23

Dependent claims

An electronic component containing a buried layer element in an integrated circuit (IC), comprising:

a buried layer element of a first conductivity type formed at an interface between a semiconductor substrate of a second conductivity type and an epitaxial layer of said second conductivity type formed on a top surface of said semiconductor substrate;
and
a floating buried layer structure of said first conductivity type formed at said interface between said semiconductor substrate and said epitaxial layer laterally surrounding said buried layer element.

An IC containing an electronic component with a buried layer element, comprising:

a semiconductor substrate of a first conductive type;
an epitaxial layer of said first conductivity type formed on a top surface of said semiconductor substrate;
a buried layer element of a second conductivity type formed at an interface between said semiconductor substrate and said epitaxial layer;
a floating buried layer structure of said second conductivity type formed at said interface between said semiconductor substrate and said epitaxial layer laterally surrounding said buried layer element.

1 more element

A method of forming an IC containing an electronic component with a buried layer element, comprising the steps of:

providing a semiconductor substrate of a first conductive type;
forming an epitaxial layer of said first conductivity type on a top surface of said semiconductor substrate;
forming a buried layer element of a second conductivity type at an interface between said semiconductor substrate and said epitaxial layer;
forming a floating buried layer structure of said second conductivity type at said interface between said semiconductor substrate and said epitaxial layer laterally surrounding said buried layer element.

1 more element

Dependencies are inferred from the claim text.

Buried floating layer structure for improved breakdown

Life of this patent

Buried floating layer structure for improved breakdown

Life of this patent

Abstract

Claims23