Fin FET and method of fabricating same

A memory cell device comprising:

• a field effect transistor comprising:
• an active region and a device isolation film;
• a first recess in the device isolation film having a first gate electrode disposed therein, the first recess having a first depth measured from an uppermost surface of the active region;
• a second recess in the active region having a second gate electrode disposed therein, the second recess having a second depth measured from the uppermost surface of the active region, the second depth being less than the first depth;
• a gate insulation layer disposed between the active region and the second gate electrode;
• source/drain regions disposed in the active region on both sides of the second gate electrode;
• and
• a capacitor connected to the field effect transistor.

A semiconductor device comprising:

• an active region and a device isolation film;
• a first recess in the device isolation film having a first gate electrode disposed therein, the first recess having a first depth measured from an uppermost surface of the active region;
• a second recess in the active region having a second gate electrode disposed therein, the second recess having a second depth measured from the uppermost surface of the active region, the second depth being less than the first depth;
• a third recess in the active region having a third gate electrode disposed therein, the third recess having the second depth measured from the uppermost surface of the active region;
• a first gate insulator disposed between the active region and the second gate electrode, the first gate insulator disposed in the second recess;
• and
• a second gate insulator disposed between the active region and the third gate electrode, the second gate insulator disposed in the third recess,
• wherein the second gate electrode is a gate electrode of a first transistor formed at the active region and the third gate electrode is a gate electrode of a second transistor disposed adjacent to the first transistor at the active region, and the device further comprises,
• a shared drain region disposed in the active region between the second gate electrode and the third gate electrode;
• a first source region disposed in the active region at a side of the second gate electrode opposite the shared drain region;
• and
• a second source region disposed in the active region at a side of the third gate electrode opposite the shared drain region.