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US 8,264,032 B2Granted
Accumulation type FinFET, circuits and fabrication method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChih Chieh Yeh, Chih-Sheng Chang, Clement Hsingjen Wann
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Abstract
A FinFET includes a substrate and a fin structure on the substrate. The fin structure includes a channel between a source and a drain, wherein the source, the drain, and the channel have the first type dopant. The channel includes a Ge, SiGe, or III-V semiconductor. A gate dielectric layer is located over the channel and a gate is located over the gate dielectric layer.
Claims20
A FinFET, comprising:
- a substrate;
- a fin structure on the substrate, the fin structure including a channel between a source and a drain, wherein the source, the drain, and the channel have a first type dopant, and the channel comprises at least one of a Ge, SiGe, or III-V semiconductor, and the channel has a dopant concentration between about 1e18 cm−3 and about 3e18 cm−3;
- a gate dielectric layer over the channel;
- and
- a gate over the gate dielectric layer.
2 more elements
A method for forming a FinFET, comprising:
- forming a fin structure on a substrate, the fin structure including a channel between a source and a drain, wherein the source, the drain, and the channel have a first type dopant, and the channel comprises at least one of a Ge, SiGe, or III-V semiconductor, and the channel has a dopant concentration between about 1e18 cm−3 and about 3e18 cm−3;
- forming a gate dielectric layer over the channel;
- and
- forming a gate over the gate dielectric layer.
1 more element
An integrated circuit, comprising:
- a substrate;
- a dummy pattern including at least one of a first fin structure on the substrate, the first fin structure comprising a first channel between a first source and a first drain, wherein the first source, the first drain, and the first channel have a first type dopant;
- and
- a FinFET over the substrate, the FinFET including:
- a second fin structure on the substrate, the second fin structure including a second channel between a second source and a second drain, wherein the second source, the second drain, and the second channel have the first type dopant, and the second channel comprises at least one of a Ge, SiGe, or III-V semiconductor, and wherein at least one of the second source and the second drain comprises at least one of a Ge, SiGe, Si, GeSn, SiGeSn, or III-V semiconductor;
- a gate dielectric layer over the second channel;
- and
- a gate over the gate dielectric layer.
5 more elements
Dependencies are inferred from the claim text.